Leopold Toetsch wrote: > Mitchell N Charity <[EMAIL PROTECTED]> wrote: > > > Perhaps it is time to get "multiple gc regimes can coexist" working? > > Sounds good, but AFAIK doesn't work - or isn't practical. I can only > imagine to have some #defines in place, to switch/test different > schemes, as currently LEA allocator.
Intel developed the Open Runtime Platform wich has multiple coexisting JITs and GCs: http://www.intel.com/technology/itj/2003/volume07issue01/art01_orp/p01_abstr act.htm http://www.intel.com/technology/itj/2003/volume07issue01/art01_orp/vol7iss1_ art01.pdf > > In addition to complexity cost, downsides include an extra test/indirection > > so multiple PMC layouts can coexist. > > That's the problem. When you touch each PMC during a DOD run, you defeat > e.g. my current approach with separated DOD flags, where PMC memory is > not touched. > > > Mitchell > > leo > Alin
