Why would a software machine closely emulating CISC architecture be expected to execute as efficiently on RISC and CISC machines?
Does it make any sense to create a low-level machine modeled on one-architecture instead of a high-level architecture which can flexibly optimize to either architecture? Also, I thought Parrot was not "stack-based" If that is the case then why does Overview.pod say this: "Registers will be stored in register frames, which can be pushed and popped onto the register stack. For instance, a subroutine or a block might need its own register frame."