Benjamin Goldberg <[EMAIL PROTECTED]> wrote:
> Not "the next instruction" ... the next *branch* instruction. And only
> replace those branch instructions which could be loops.
Works. Many thanks for the input.
I have now running this:
1) Initialization:
- normal core: build op_func_table with all opcode #4 [1]
- CG core: build ops_addr[] filled with this opcode
- prederef cores: build a list of (backward) branch instructions
and the opcode at that offset
2) When an events gets scheduled (signal handler) it calls the running
core with:
interpreter->op_func_table =
init_func(interpreter, OPLIB_SET_CHK_EV_FT)->op_func_table;
This replaces for normal and CG core the op_func_table or the
ops_addr with that from 1)
Prederefed cores get on all branch instruction from the list built
in 1) an opcode #4 patched.
3) So when the next instruction (normal, CG core) or the branch
instruction (prederefed cores) gets executed, first the op_func_table
or the patched instructions are restored and then the event handler
can be called.
This now works for all cores (except JIT[2]). It doesn't have any runtime
penalty for an extra check if events are due.
[1] This opcode (check_event__) calls the actual event handling code
and returns the same address, i.e. doesn't advance the PC.
[2] We could do the same here, but this needs cache sync for ARM and PPC,
which may or may not be allowed in signal code.
Still needs some cleanup ...
leo
