From 5e29fdc048f354c3353da40f00ebd7718be43f11 Mon Sep 17 00:00:00 2001 From: Takashi Menjo Date: Thu, 28 Oct 2021 13:35:28 +0900 Subject: [PATCH v4 7/9] Ensure WAL mappings before assertion --- src/backend/access/transam/xlog.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/backend/access/transam/xlog.c b/src/backend/access/transam/xlog.c index e3e28fb9d3..9753b7b24f 100644 --- a/src/backend/access/transam/xlog.c +++ b/src/backend/access/transam/xlog.c @@ -1913,6 +1913,23 @@ GetXLogBuffer(XLogRecPtr ptr) */ if (ptr / XLOG_BLCKSZ == cachedPage) { + /* + * Ensure WAL mappings before assersion. + * + * cachedPos should be recaluculated because it has been probably + * invalidated due to WAL remapping. This should be done even if + * openLogSegNo seems not to change because the address of the + * mapping could have changed (ABA problem). + */ + if (wal_pmem_map) + { + endptr = ptr - ptr % XLOG_BLCKSZ + XLOG_BLCKSZ; + openLogSegNo = PmemXLogEnsurePrevMapped(endptr); + cachedPos = PmemXLogGetBufferPages() + + (Size) XLogSegmentOffset(endptr - XLOG_BLCKSZ, + wal_segment_size); + } + Assert(((XLogPageHeader) cachedPos)->xlp_magic == XLOG_PAGE_MAGIC); Assert(((XLogPageHeader) cachedPos)->xlp_pageaddr == ptr - (ptr % XLOG_BLCKSZ)); return cachedPos + ptr % XLOG_BLCKSZ; -- 2.25.1