On Sun, Oct 12, 2025 at 2:00 AM Alexander Lakhin <[email protected]> wrote: > I've managed to reproduce it using qemu-system-riscv64 with Debian trixie
Huh, that's interesting. What is the host architecture? When I saw that error myself and wondered about memory order, I dismissed the idea of trying with qemu, figuring that my x86 host's TSO would affect the coherency, but thinking again about that... I guess the compiler might still reorder during riscv codegen if there is something wrong with the barrier support, and even if it doesn't, the binary translation to x86 might also feel free to reorder stuff if there are no barrier instructions to prevent it? Or maybe that doesn't happen but your host is ARM?
