Hi, Thanks for pointing me to the patch submission guidelines.
Attached is v2. The code change is unchanged from v1. This revision reformats the commit message and adds the missing submission, validation, platform, and performance information. The patch is intended for review and application against PostgreSQL master. It defines PG_HAVE_8BYTE_SINGLE_COPY_ATOMICITY on RV64, allowing the generic pg_atomic_read_u64() and pg_atomic_write_u64() implementations to use naturally aligned plain loads and stores instead of compare/exchange loops. RV32 remains unchanged. Validation was performed on PostgreSQL commit 86f7c82cf1023e3599f40f939727791a7090cd44. Test environment: - Hardware: SpacemiT K3 / spacemit-x100 - Architecture: RV64GC - Compiler: GCC 12.3.1 - CFLAGS: -O2 -g -march=rv64gc -mabi=lp64d Results: - configure/build/install: passed - PostgreSQL regression tests: 240/240 passed - PinBuffer targeted stress test: passed - pg_amcheck: passed - 80-client/40-thread/60-second soak tests: no failures - disassembly confirmed that the target read path changed from an lr.d/sc.d loop to ld, while state-updating CAS paths retained LR/SC The paired pgbench campaign covered 13 workload and concurrency conditions, with 10 interleaved baseline/candidate runs per condition, for a total of 130 pairs. Each pair used the same seed, and the baseline/candidate execution order was alternated. Results: - 114/130 pairs favored the patched build - mean improvement: 1.680% - median improvement: 1.665% - bootstrap median 95% CI: [1.358%, 1.897%] These measurements were obtained from one RV64 system and do not imply the same performance improvement on every RV64 implementation. No new SQL regression test is included because this change has no SQL-visible behavior. No user-facing documentation change is needed because this is an internal architecture-specific optimization. Changes since v1: - reformatted and clarified the commit message - added branch and submission status - added platform and validation information - added performance methodology and results - clarified the scope of the performance measurements Regards, Hongyan Wang -----原始邮件----- 发件人:"wenhui qiu" <[email protected]> 发送时间:2026-09-17 11:30:18 (星期四) 收件人: wanghongyan <[email protected]> 抄送: [email protected], "Ni Jincheng" <[email protected]>, Yuansheng <[email protected]> 主题: Re: [PATCH v1] Optimize 64-bit atomic access on RV64 Hi Wanghongyan You can follow up this document : https://wiki.postgresql.org/wiki/Submitting_a_Patch Thanks
From 6d3eb7f1dd778b5795d331685400e43381d68bf9 Mon Sep 17 00:00:00 2001 From: wanghongyan <[email protected]> Date: Wed, 16 Sep 2026 16:29:35 +0800 Subject: [PATCH v2] Optimize 64-bit atomic access on RV64 RV64 guarantees that naturally aligned XLEN-wide loads and stores are atomic. Teach PostgreSQL about that property by defining PG_HAVE_8BYTE_SINGLE_COPY_ATOMICITY in a new RISC-V atomics header. This allows the generic pg_atomic_read_u64() and pg_atomic_write_u64() implementations to use plain loads and stores instead of compare/exchange loops on RV64. Keep RV32 on the existing generic fallback. Co-authored-by: Ni Jincheng <[email protected]> Co-authored-by: Yuansheng <[email protected]> --- src/include/port/atomics.h | 2 ++ src/include/port/atomics/arch-riscv.h | 26 ++++++++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 src/include/port/atomics/arch-riscv.h diff --git a/src/include/port/atomics.h b/src/include/port/atomics.h index a605ea81d07..985f4e2416f 100644 --- a/src/include/port/atomics.h +++ b/src/include/port/atomics.h @@ -69,6 +69,8 @@ #include "port/atomics/arch-x86.h" #elif defined(__powerpc__) || defined(__powerpc64__) #include "port/atomics/arch-ppc.h" +#elif defined(__riscv) +#include "port/atomics/arch-riscv.h" #endif /* diff --git a/src/include/port/atomics/arch-riscv.h b/src/include/port/atomics/arch-riscv.h new file mode 100644 index 00000000000..761a9811cff --- /dev/null +++ b/src/include/port/atomics/arch-riscv.h @@ -0,0 +1,26 @@ +/*------------------------------------------------------------------------- + * + * arch-riscv.h + * Atomic operations considerations specific to RISC-V + * + * Portions Copyright (c) 1996-2026, PostgreSQL Global Development Group + * + * src/include/port/atomics/arch-riscv.h + * + *------------------------------------------------------------------------- + */ + +/* intentionally no include guards, should only be included by atomics.h */ +#ifndef INSIDE_ATOMICS_H +#error "should be included via atomics.h" +#endif + +/* + * The RV64 base ISA guarantees naturally aligned XLEN-bit loads and stores + * are atomic. PostgreSQL's pg_atomic_uint64 objects are naturally aligned, + * so the generic implementation may use a single plain load/store rather + * than a compare/exchange loop. RV32 retains the generic fallback. + */ +#if __riscv_xlen == 64 +#define PG_HAVE_8BYTE_SINGLE_COPY_ATOMICITY +#endif -- 2.43.0
