That weird one from Intel Itanium. Why?, because it's not a 64bit
ISA. They use a smaller Instruction Set Architecture than 64bit,
which is a Good Thing for caching purposes. (This is not an
endorsement of Itanium, I haven't looked closely enough to make an
accurate assessment)
In truth, I wouldn't pick a 64bit processor anyway. Having 64bit or
even 128bit registers for the occasional high precision operation is
one thing, but getting your code bloated to the nth degree as part of
it is not a good trade off given current technologies.
There hasn't been a good 64bit ISA brought to the table yet I think.
What I would like to see in such an ISA is the ability to express
more than one operation per instruction. I have this ISA that I
wrote out that was a 32bit ISA, but part of me wants to expand it to
64, and the idea behind it is singular sized instructions that can be
tagged with "sub ops". Basically the first bit determined whether it
was a "true 32bit instruction", i.e. did one thing in one
instruction, or whether it was a micro op instruction. The micro op
instructions would have encoded within them 3 seperate register to
register arithmetic operations, or 3 stack operations performed by
baselining the stack with one of the registers. (ala stmia, ldmia of
ARM fame)
If this idea were expanded out to 64 bits, then you would probably
have 3 different "multi op" types, one that did 6 ops per insn, 3 and
1. One op insns would probably be mostly reserved for something like
loading registers. (Loading 64bit registers can be less than fun)
The key for quick arithmetics IMHO is to be able to load *two* full
sized registers and perform an operation between them in 3
instructions. The problem today is bandwidth into the CPU, the only
way to solve it is with better memory technologies, or more expresive
ISAs..., since the bandwidth problem isn't getting solved anytime
soon we might as well get into expresiveness.
Thanks,
Shane Nay.
Anyway, ALUs are tiny structures so this could be fun.
BTW- quick arithmetics in the ISA I threw together would be done this
way-
lui r0, #0x0123456 @lui has 28 bits of expresiveness
lui r1, #0x0123456
{ ori r0 #0x7, ori r1 #0x7, add r0, r1}
/* The add op places the result in the first mentioned register, so
the result would be r0=0x02468ACE , r1=0x01234567*/
(Full add register to register with a 32bit insn size, 32bit register
size total code and data- 32bit*3=96bit. In ARM this would be 3
instructions and 2 32bit data pieces, so 160bits, not to mention the
cache hit involved with ldr)
On Saturday 16 February 2002 21:14, Dave Poirier wrote:
> I've been doing a bit of thinking here, and I would like to have
> your opinion on something.
>
> If you had to choose a 64bit cpu for its instruction set (not it's
> speed, nor its availability), which one would you choose?
>
> Any suggestion and url would be greatly appreciated, thanks.
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