Sorry, I forgot to address the every-other-one concern. The MMX registers are 64-bits, so you can only do 1 double at a time. Those instructions only require 8-byte aligned memory. The SSE instructions use 128-bit registers, so they take 2 doubles at a time. As long as the first one is 16-byte aligned, you can iterate through on 16-byte (128 bits) chunks, and you'll be good. That's why element 0 should be 128-aligned.
If it's not, the processor will either have an alignment fault (in the instruction requires alignment) or will do a bunch of split-loads across cache lines, which kill performance. One other thought: If you wanted to be tricky, you could do a general, 4-byte allocation and based on the address you get, assign your storage pointer to the next 128-aligned address. But you're offloading to run-time lot's of housekeeping. Again, maybe tolerable for just these large arrays. But it starts to add a lot of corner cases. Walter might have some good suggestions here. Jason ----- Original Message ---- > From: Steve Schveighoffer < > A question then -- let's say you have an array of > doubles, which are 8 bytes wide, and you want to > use these SSE instructions. Even if the first one is aligned on a 16-byte > boundary, wouldn't every other double be > misaligned? _______________________________________________ phobos mailing list [email protected] http://lists.puremagic.com/mailman/listinfo/phobos
