On Fri, May 22, 2015 at 04:07:03PM -0300, Fernando Seiti Furusato wrote: > Hi Lennart. > > Your questions really got me thinking. But I made some researching. > > On 05/22/2015 02:54 PM, Lennart Sorensen wrote: > >Isn't altivec always big endian? If so, that would make running altivec > >code while in little endian mode interesting. > I believe that depends mostly on the implementation. > The implications of endianness differences for the instructions themselves can > be checked out on Power ABI Specification[1]. > > > >I was under the impression that ppc64le used vsx instead of altivec. > Afaik, vsx is actually an extension to SIMD processing for POWER. It was > introduced with POWER7 machines. > > Thanks! > > [1] > https://www-03.ibm.com/technologyconnect/tgcm/TGCMFileServlet.wss/ABI64BitOpenPOWER_21July2014_pub%283%29.pdf?id=B81AEC1A37F5DAF185257C3E004E8845&linkid=1n0000&c_t=c9xw7v5dzsj7gt1ifgf4cjbcnskqptmr
That seems to require registration. :) This presentation seemed to indicate that at least there are some biases towards big endian in the vector instructions: http://llvm.org/devmtg/2014-10/Slides/Schmidt-SupportingVectorProgramming.pdf -- Len Sorensen _______________________________________________ Pixman mailing list Pixman@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/pixman
