Author: marcus Date: Sat Jun 23 18:28:39 2007 GMT
Module: SOURCES Tag: HEAD
---- Log message:
- http://download.nvidia.com/XFree86/nforce/1.21/NFORCE-Linux-x86-1.21.zip
---- Files affected:
SOURCES:
linux-nvidia.patch (NONE -> 1.1) (NEW)
---- Diffs:
================================================================
Index: SOURCES/linux-nvidia.patch
diff -u /dev/null SOURCES/linux-nvidia.patch:1.1
--- /dev/null Sat Jun 23 20:28:39 2007
+++ SOURCES/linux-nvidia.patch Sat Jun 23 20:28:34 2007
@@ -0,0 +1,8077 @@
+diff -uNr linux-2.6.16.orig/drivers/net/forcedeth.c
linux-2.6.16/drivers/net/forcedeth.c
+--- linux-2.6.16.orig/drivers/net/forcedeth.c 2007-06-23 20:16:01.572248000
+0200
++++ linux-2.6.16/drivers/net/forcedeth.c 2006-10-21 14:44:00.000000000
+0200
+@@ -102,6 +102,17 @@
+ * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
+ * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
+ * 0.49: 10 Dec 2005: Fix tso for large buffers.
++ * 0.50: 20 Jan 2006: Add 8021pq tagging support.
++ * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
++ * 0.52: 20 Jan 2006: Add MSI/MSIX support.
++ * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
++ * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
++ * 0.55: 22 Mar 2006: Add flow control (pause frame).
++ * 0.56: 22 Mar 2006: Additional ethtool and moduleparam support.
++ * 0.57: 14 May 2006: Moved mac address writes to nv_probe and nv_remove.
++ * 0.58: 20 May 2006: Optimized rx and tx data paths.
++ * 0.59: 31 May 2006: Added support for sideband management unit.
++ * 0.60: 31 May 2006: Added support for recoverable error.
+ *
+ * Known bugs:
+ * We suspect that on some hardware no TX done interrupts are generated.
+@@ -113,7 +124,7 @@
+ * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
+ * superfluous timer interrupts from the nic.
+ */
+-#define FORCEDETH_VERSION "0.49"
++#define FORCEDETH_VERSION "0.60-Driver Package V1.21"
+ #define DRV_NAME "forcedeth"
+
+ #include <linux/module.h>
+@@ -131,34 +142,189 @@
+ #include <linux/random.h>
+ #include <linux/init.h>
+ #include <linux/if_vlan.h>
++#include <linux/rtnetlink.h>
++#include <linux/version.h>
++
++#define RHES3 0
++#define SLES9 1
++#define RHES4 2
++#define SUSE10 3
++#define FEDORA5 4
++
++
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13)
++#define NVVER FEDORA5
++#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
++#define NVVER SUSE10
++#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,6)
++#define NVVER RHES4
++#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
++#define NVVER SLES9
++#else
++#define NVVER RHES3
++#endif
++
++#if NVVER > RHES3
++#include <linux/dma-mapping.h>
++#else
++#include <linux/forcedeth-compat.h>
++#endif
+
+ #include <asm/irq.h>
+ #include <asm/io.h>
+ #include <asm/uaccess.h>
+ #include <asm/system.h>
+
+-#if 0
++#ifdef NVLAN_DEBUG
+ #define dprintk printk
+ #else
+ #define dprintk(x...) do { } while (0)
+ #endif
+
++/* it should add in pci_ids.h */
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_12
++#define PCI_DEVICE_ID_NVIDIA_NVENET_12 0x0268
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_13
++#define PCI_DEVICE_ID_NVIDIA_NVENET_13 0x0269
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_14
++#define PCI_DEVICE_ID_NVIDIA_NVENET_14 0x0372
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_15
++#define PCI_DEVICE_ID_NVIDIA_NVENET_15 0x0373
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_16
++#define PCI_DEVICE_ID_NVIDIA_NVENET_16 0x03E5
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_17
++#define PCI_DEVICE_ID_NVIDIA_NVENET_17 0x03E6
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_18
++#define PCI_DEVICE_ID_NVIDIA_NVENET_18 0x03EE
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_19
++#define PCI_DEVICE_ID_NVIDIA_NVENET_19 0x03EF
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_20
++#define PCI_DEVICE_ID_NVIDIA_NVENET_20 0x0450
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_21
++#define PCI_DEVICE_ID_NVIDIA_NVENET_21 0x0451
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_22
++#define PCI_DEVICE_ID_NVIDIA_NVENET_22 0x0452
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_23
++#define PCI_DEVICE_ID_NVIDIA_NVENET_23 0x0453
++#endif
++
++/* it should add in mii.h */
++#ifndef ADVERTISE_1000HALF
++#define ADVERTISE_1000HALF 0x0100
++#endif
++#ifndef ADVERTISE_1000FULL
++#define ADVERTISE_1000FULL 0x0200
++#endif
++#ifndef ADVERTISE_PAUSE_CAP
++#define ADVERTISE_PAUSE_CAP 0x0400
++#endif
++#ifndef ADVERTISE_PAUSE_ASYM
++#define ADVERTISE_PAUSE_ASYM 0x0800
++#endif
++#ifndef MII_CTRL1000
++#define MII_CTRL1000 0x09
++#endif
++#ifndef MII_STAT1000
++#define MII_STAT1000 0x0A
++#endif
++#ifndef LPA_1000FULL
++#define LPA_1000FULL 0x0800
++#endif
++#ifndef LPA_1000HALF
++#define LPA_1000HALF 0x0400
++#endif
++#ifndef LPA_PAUSE_CAP
++#define LPA_PAUSE_CAP 0x0400
++#endif
++#ifndef LPA_PAUSE_ASYM
++#define LPA_PAUSE_ASYM 0x0800
++#endif
++#ifndef BMCR_SPEED1000
++#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000)
*/
++#endif
++
++#ifndef NETDEV_TX_OK
++#define NETDEV_TX_OK 0 /* driver took care of packet */
++#endif
++
++#ifndef NETDEV_TX_BUSY
++#define NETDEV_TX_BUSY 1 /* driver tx path was busy*/
++#endif
++
++#ifndef DMA_39BIT_MASK
++#define DMA_39BIT_MASK 0x0000007fffffffffULL
++#endif
++
++#ifndef __iomem
++#define __iomem
++#endif
++
++/* rx/tx mac addr + type + vlan + align + slack*/
++#ifndef RX_NIC_BUFSIZE
++#define RX_NIC_BUFSIZE (ETH_DATA_LEN + 64)
++#endif
++/* even more slack */
++#ifndef RX_ALLOC_BUFSIZE
++#define RX_ALLOC_BUFSIZE (ETH_DATA_LEN + 128)
++#endif
++
++#ifndef PCI_DEVICE
++#define PCI_DEVICE(vend,dev) \
++ .vendor = (vend), .device = (dev), \
++ .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
++#endif
++
++#if NVVER < RHES4
++struct msix_entry {
++ u16 vector; /* kernel uses to write allocated vector */
++ u16 entry; /* driver uses to specify entry, OS writes */
++};
++#endif
+
+ /*
+ * Hardware access:
+ */
+
+-#define DEV_NEED_TIMERIRQ 0x0000 /* work-around for Wake-On-Lan */
+-#define DEV_NEED_TIMERIRQ_ORIG 0x0001 /* set the timer irq flag in
the irq mask */
++#define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq
mask */
+ #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the
timer irq */
+ #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and
needs packet format 2 */
+ #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
+ #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum
offloads */
++#define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and
striping */
++#define DEV_HAS_MSI 0x0040 /* device supports MSI */
++#define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */
++#define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */
++#define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */
++#define DEV_HAS_STATISTICS 0x0400 /* device supports hw statistics */
++#define DEV_HAS_TEST_EXTENDED 0x0800 /* device supports extended
diagnostic test */
++#define DEV_HAS_MGMT_UNIT 0x1000 /* device supports management unit */
++
++#define NVIDIA_ETHERNET_ID(deviceid,nv_driver_data) {\
++ .vendor = PCI_VENDOR_ID_NVIDIA, \
++ .device = deviceid, \
++ .subvendor = PCI_ANY_ID, \
++ .subdevice = PCI_ANY_ID, \
++ .driver_data = nv_driver_data, \
++ },
++
++#define Mv_LED_Control 16
++#define Mv_Page_Address 22
+
+ enum {
+ NvRegIrqStatus = 0x000,
+ #define NVREG_IRQSTAT_MIIEVENT 0x040
+-#define NVREG_IRQSTAT_MASK 0x1ff
++#define NVREG_IRQSTAT_MASK 0x81ff
+ NvRegIrqMask = 0x004,
+ #define NVREG_IRQ_RX_ERROR 0x0001
+ #define NVREG_IRQ_RX 0x0002
+@@ -167,14 +333,18 @@
+ #define NVREG_IRQ_TX_OK 0x0010
+ #define NVREG_IRQ_TIMER 0x0020
+ #define NVREG_IRQ_LINK 0x0040
+-#define NVREG_IRQ_TX_ERROR 0x0080
+-#define NVREG_IRQ_TX1 0x0100
++#define NVREG_IRQ_RX_FORCED 0x0080
++#define NVREG_IRQ_TX_FORCED 0x0100
++#define NVREG_IRQ_RECOVER_ERROR 0x8000
+ #define NVREG_IRQMASK_THROUGHPUT 0x00df
+ #define NVREG_IRQMASK_CPU 0x0040
++#define NVREG_IRQ_TX_ALL
(NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
++#define NVREG_IRQ_RX_ALL
(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
++#define NVREG_IRQ_OTHER
(NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
+
+ #define NVREG_IRQ_UNKNOWN
(~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
+-
NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX_ERROR| \
+- NVREG_IRQ_TX1))
++
NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
++
NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
+
+ NvRegUnknownSetupReg6 = 0x008,
+ #define NVREG_UNKSETUP6_VAL 3
+@@ -186,25 +356,45 @@
+ NvRegPollingInterval = 0x00c,
+ #define NVREG_POLL_DEFAULT_THROUGHPUT 970
+ #define NVREG_POLL_DEFAULT_CPU 13
++ NvRegMSIMap0 = 0x020,
++ NvRegMSIMap1 = 0x024,
++ NvRegMSIIrqMask = 0x030,
++#define NVREG_MSI_VECTOR_0_ENABLED 0x01
+ NvRegMisc1 = 0x080,
++#define NVREG_MISC1_PAUSE_TX 0x01
+ #define NVREG_MISC1_HD 0x02
+ #define NVREG_MISC1_FORCE 0x3b0f3c
+
++ NvRegMacReset = 0x3c,
++#define NVREG_MAC_RESET_ASSERT 0x0F3
+ NvRegTransmitterControl = 0x084,
+ #define NVREG_XMITCTL_START 0x01
++#define NVREG_XMITCTL_MGMT_ST 0x40000000
++#define NVREG_XMITCTL_SYNC_MASK 0x000f0000
++#define NVREG_XMITCTL_SYNC_NOT_READY 0x0
++#define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
++#define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
++#define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
++#define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
++#define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
++#define NVREG_XMITCTL_HOST_LOADED 0x00004000
++#define NVREG_XMITCTL_TX_PATH_EN 0x01000000
+ NvRegTransmitterStatus = 0x088,
+ #define NVREG_XMITSTAT_BUSY 0x01
+
+ NvRegPacketFilterFlags = 0x8c,
+-#define NVREG_PFF_ALWAYS 0x7F0008
++#define NVREG_PFF_PAUSE_RX 0x08
++#define NVREG_PFF_ALWAYS 0x7F0000
+ #define NVREG_PFF_PROMISC 0x80
+ #define NVREG_PFF_MYADDR 0x20
++#define NVREG_PFF_LOOPBACK 0x10
+
+ NvRegOffloadConfig = 0x90,
+ #define NVREG_OFFLOAD_HOMEPHY 0x601
+ #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
+ NvRegReceiverControl = 0x094,
+ #define NVREG_RCVCTL_START 0x01
++#define NVREG_RCVCTL_RX_PATH_EN 0x01000000
+ NvRegReceiverStatus = 0x98,
+ #define NVREG_RCVSTAT_BUSY 0x01
+
+@@ -214,10 +404,12 @@
+ #define NVREG_RNDSEED_FORCE2 0x2d00
+ #define NVREG_RNDSEED_FORCE3 0x7400
+
+- NvRegUnknownSetupReg1 = 0xA0,
+-#define NVREG_UNKSETUP1_VAL 0x16070f
+- NvRegUnknownSetupReg2 = 0xA4,
+-#define NVREG_UNKSETUP2_VAL 0x16
++ NvRegTxDeferral = 0xA0,
++#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
++#define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
++#define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
++ NvRegRxDeferral = 0xA4,
++#define NVREG_RX_DEFERRAL_DEFAULT 0x16
+ NvRegMacAddrA = 0xA8,
+ NvRegMacAddrB = 0xAC,
+ NvRegMulticastAddrA = 0xB0,
+@@ -234,7 +426,8 @@
+ NvRegRingSizes = 0x108,
+ #define NVREG_RINGSZ_TXSHIFT 0
+ #define NVREG_RINGSZ_RXSHIFT 16
+- NvRegUnknownTransmitterReg = 0x10c,
++ NvRegTransmitPoll = 0x10c,
++#define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
+ NvRegLinkSpeed = 0x110,
+ #define NVREG_LINKSPEED_FORCE 0x10000
+ #define NVREG_LINKSPEED_10 1000
+@@ -243,8 +436,10 @@
+ #define NVREG_LINKSPEED_MASK (0xFFF)
+ NvRegUnknownSetupReg5 = 0x130,
+ #define NVREG_UNKSETUP5_BIT31 (1<<31)
+- NvRegUnknownSetupReg3 = 0x13c,
+-#define NVREG_UNKSETUP3_VAL1 0x200010
++ NvRegTxWatermark = 0x13c,
++#define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
++#define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
++#define NVREG_TX_WM_DESC2_3_1000 0xfe08000
+ NvRegTxRxControl = 0x144,
+ #define NVREG_TXRXCTL_KICK 0x0001
+ #define NVREG_TXRXCTL_BIT1 0x0002
+@@ -253,15 +448,22 @@
+ #define NVREG_TXRXCTL_RESET 0x0010
+ #define NVREG_TXRXCTL_RXCHECK 0x0400
+ #define NVREG_TXRXCTL_DESC_1 0
+-#define NVREG_TXRXCTL_DESC_2 0x02100
+-#define NVREG_TXRXCTL_DESC_3 0x02200
++#define NVREG_TXRXCTL_DESC_2 0x002100
++#define NVREG_TXRXCTL_DESC_3 0xc02200
++#define NVREG_TXRXCTL_VLANSTRIP 0x00040
++#define NVREG_TXRXCTL_VLANINS 0x00080
++ NvRegTxRingPhysAddrHigh = 0x148,
++ NvRegRxRingPhysAddrHigh = 0x14C,
++ NvRegTxPauseFrame = 0x170,
++#define NVREG_TX_PAUSEFRAME_DISABLE 0x1ff0080
++#define NVREG_TX_PAUSEFRAME_ENABLE 0x0c00030
+ NvRegMIIStatus = 0x180,
+ #define NVREG_MIISTAT_ERROR 0x0001
+ #define NVREG_MIISTAT_LINKCHANGE 0x0008
+ #define NVREG_MIISTAT_MASK 0x000f
+ #define NVREG_MIISTAT_MASK2 0x000f
+- NvRegUnknownSetupReg4 = 0x184,
+-#define NVREG_UNKSETUP4_VAL 8
++ NvRegMIIMask = 0x184,
++#define NVREG_MII_LINKCHANGE 0x0008
+
+ NvRegAdapterControl = 0x188,
+ #define NVREG_ADAPTCTL_START 0x02
+@@ -291,6 +493,7 @@
+ #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
+
+ NvRegPatternCRC = 0x204,
++#define NV_UNKNOWN_VAL 0x01
+ NvRegPatternMask = 0x208,
+ NvRegPowerCap = 0x268,
+ #define NVREG_POWERCAP_D3SUPP (1<<30)
+@@ -304,6 +507,43 @@
+ #define NVREG_POWERSTATE_D1 0x0001
+ #define NVREG_POWERSTATE_D2 0x0002
+ #define NVREG_POWERSTATE_D3 0x0003
++ NvRegTxCnt = 0x280,
++ NvRegTxZeroReXmt = 0x284,
++ NvRegTxOneReXmt = 0x288,
++ NvRegTxManyReXmt = 0x28c,
++ NvRegTxLateCol = 0x290,
++ NvRegTxUnderflow = 0x294,
++ NvRegTxLossCarrier = 0x298,
++ NvRegTxExcessDef = 0x29c,
++ NvRegTxRetryErr = 0x2a0,
++ NvRegRxFrameErr = 0x2a4,
++ NvRegRxExtraByte = 0x2a8,
++ NvRegRxLateCol = 0x2ac,
++ NvRegRxRunt = 0x2b0,
++ NvRegRxFrameTooLong = 0x2b4,
++ NvRegRxOverflow = 0x2b8,
++ NvRegRxFCSErr = 0x2bc,
++ NvRegRxFrameAlignErr = 0x2c0,
++ NvRegRxLenErr = 0x2c4,
++ NvRegRxUnicast = 0x2c8,
++ NvRegRxMulticast = 0x2cc,
++ NvRegRxBroadcast = 0x2d0,
++ NvRegTxDef = 0x2d4,
++ NvRegTxFrame = 0x2d8,
++ NvRegRxCnt = 0x2dc,
++ NvRegTxPause = 0x2e0,
++ NvRegRxPause = 0x2e4,
++ NvRegRxDropFrame = 0x2e8,
++
++ NvRegVlanControl = 0x300,
++#define NVREG_VLANCONTROL_ENABLE 0x2000
++ NvRegMSIXMap0 = 0x3e0,
++ NvRegMSIXMap1 = 0x3e4,
++ NvRegMSIXIrqStatus = 0x3f0,
++
++ NvRegPowerState2 = 0x600,
++#define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
++#define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
+ };
+
+ /* Big endian: should work, but is untested */
+@@ -315,7 +555,7 @@
+ struct ring_desc_ex {
+ u32 PacketBufferHigh;
+ u32 PacketBufferLow;
+- u32 Reserved;
++ u32 TxVlan;
+ u32 FlagLen;
+ };
+
+@@ -336,7 +576,7 @@
+ #define NV_TX_CARRIERLOST (1<<27)
+ #define NV_TX_LATECOLLISION (1<<28)
+ #define NV_TX_UNDERFLOW (1<<29)
+-#define NV_TX_ERROR (1<<30)
++#define NV_TX_ERROR (1<<30) /* logical OR of all errors */
+ #define NV_TX_VALID (1<<31)
+
+ #define NV_TX2_LASTPACKET (1<<29)
+@@ -347,7 +587,7 @@
+ #define NV_TX2_LATECOLLISION (1<<27)
+ #define NV_TX2_UNDERFLOW (1<<28)
+ /* error and valid are the same for both */
+-#define NV_TX2_ERROR (1<<30)
++#define NV_TX2_ERROR (1<<30) /* logical OR of all errors */
+ #define NV_TX2_VALID (1<<31)
+ #define NV_TX2_TSO (1<<28)
+ #define NV_TX2_TSO_SHIFT 14
+@@ -356,6 +596,8 @@
+ #define NV_TX2_CHECKSUM_L3 (1<<27)
+ #define NV_TX2_CHECKSUM_L4 (1<<26)
+
++#define NV_TX3_VLAN_TAG_PRESENT (1<<18)
++
+ #define NV_RX_DESCRIPTORVALID (1<<16)
+ #define NV_RX_MISSEDFRAME (1<<17)
+ #define NV_RX_SUBSTRACT1 (1<<18)
+@@ -366,7 +608,7 @@
+ #define NV_RX_CRCERR (1<<27)
+ #define NV_RX_OVERFLOW (1<<28)
+ #define NV_RX_FRAMINGERR (1<<29)
+-#define NV_RX_ERROR (1<<30)
++#define NV_RX_ERROR (1<<30) /* logical OR of all errors */
+ #define NV_RX_AVAIL (1<<31)
+
+ #define NV_RX2_CHECKSUMMASK (0x1C000000)
+@@ -383,11 +625,15 @@
+ #define NV_RX2_OVERFLOW (1<<23)
+ #define NV_RX2_FRAMINGERR (1<<24)
+ /* error and avail are the same for both */
+-#define NV_RX2_ERROR (1<<30)
++#define NV_RX2_ERROR (1<<30) /* logical OR of all errors */
+ #define NV_RX2_AVAIL (1<<31)
+
++#define NV_RX3_VLAN_TAG_PRESENT (1<<16)
++#define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
++
+ /* Miscelaneous hardware related defines: */
+-#define NV_PCI_REGSZ 0x270
++#define NV_PCI_REGSZ_VER1 0x270
++#define NV_PCI_REGSZ_VER2 0x604
+
+ /* various timeout delays: all in usec */
+ #define NV_TXRX_RESET_DELAY 4
+@@ -404,6 +650,7 @@
+ #define NV_MIIBUSY_DELAY 50
+ #define NV_MIIPHY_DELAY 10
+ #define NV_MIIPHY_DELAYMAX 10000
++#define NV_MAC_RESET_DELAY 64
+
+ #define NV_WAKEUPPATTERNS 5
+ #define NV_WAKEUPMASKENTRIES 4
+@@ -411,16 +658,18 @@
+ /* General driver defaults */
+ #define NV_WATCHDOG_TIMEO (5*HZ)
+
+-#define RX_RING 128
+-#define TX_RING 256
++#define RX_RING_DEFAULT 128
++#define TX_RING_DEFAULT 64
++#define RX_RING_MIN RX_RING_DEFAULT
++#define TX_RING_MIN TX_RING_DEFAULT
++#define RING_MAX_DESC_VER_1 1024
++#define RING_MAX_DESC_VER_2_3 16384
+ /*
+- * If your nic mysteriously hangs then try to reduce the limits
+- * to 1/0: It might be required to set NV_TX_LASTPACKET in the
+- * last valid ring entry. But this would be impossible to
+- * implement - probably a disassembly error.
++ * Difference between the get and put pointers for the tx ring.
++ * This is used to throttle the amount of data outstanding in the
++ * tx ring.
+ */
+-#define TX_LIMIT_STOP 255
+-#define TX_LIMIT_START 254
++#define TX_LIMIT_DIFFERENCE 1
+
+ /* rx/tx mac addr + type + vlan + align + slack*/
+ #define NV_RX_HEADERS (64)
+@@ -434,6 +683,7 @@
+ #define OOM_REFILL (1+HZ/20)
+ #define POLL_WAIT (1+HZ/100)
+ #define LINK_TIMEOUT (3*HZ)
++#define STATS_INTERVAL (10*HZ)
+
+ /*
+ * desc_ver values:
+@@ -449,16 +699,37 @@
+ /* PHY defines */
+ #define PHY_OUI_MARVELL 0x5043
+ #define PHY_OUI_CICADA 0x03f1
++#define PHY_OUI_VITESSE 0x01c1
+ #define PHYID1_OUI_MASK 0x03ff
+ #define PHYID1_OUI_SHFT 6
+ #define PHYID2_OUI_MASK 0xfc00
+ #define PHYID2_OUI_SHFT 10
+-#define PHY_INIT1 0x0f000
+-#define PHY_INIT2 0x0e00
+-#define PHY_INIT3 0x01000
+-#define PHY_INIT4 0x0200
+-#define PHY_INIT5 0x0004
+-#define PHY_INIT6 0x02000
++#define PHYID2_MODEL_MASK 0x03f0
++#define PHY_MODEL_MARVELL_E3016 0x220
++#define PHY_MARVELL_E3016_INITMASK 0x0300
++#define PHY_CICADA_INIT1 0x0f000
++#define PHY_CICADA_INIT2 0x0e00
++#define PHY_CICADA_INIT3 0x01000
++#define PHY_CICADA_INIT4 0x0200
++#define PHY_CICADA_INIT5 0x0004
++#define PHY_CICADA_INIT6 0x02000
++#define PHY_VITESSE_INIT_REG1 0x1f
++#define PHY_VITESSE_INIT_REG2 0x10
++#define PHY_VITESSE_INIT_REG3 0x11
++#define PHY_VITESSE_INIT_REG4 0x12
++#define PHY_VITESSE_INIT_MSK1 0xc
++#define PHY_VITESSE_INIT_MSK2 0x0180
++#define PHY_VITESSE_INIT1 0x52b5
++#define PHY_VITESSE_INIT2 0xaf8a
++#define PHY_VITESSE_INIT3 0x8
++#define PHY_VITESSE_INIT4 0x8f8a
++#define PHY_VITESSE_INIT5 0xaf86
++#define PHY_VITESSE_INIT6 0x8f86
++#define PHY_VITESSE_INIT7 0xaf82
++#define PHY_VITESSE_INIT8 0x0100
++#define PHY_VITESSE_INIT9 0x8f82
++#define PHY_VITESSE_INIT10 0x0
++
+ #define PHY_GIGABIT 0x0100
+
+ #define PHY_TIMEOUT 0x1
+@@ -468,14 +739,148 @@
+ #define PHY_1000 0x2
+ #define PHY_HALF 0x100
+
+-/* FIXME: MII defines that should be added to <linux/mii.h> */
+-#define MII_1000BT_CR 0x09
+-#define MII_1000BT_SR 0x0a
+-#define ADVERTISE_1000FULL 0x0200
+-#define ADVERTISE_1000HALF 0x0100
+-#define LPA_1000FULL 0x0800
+-#define LPA_1000HALF 0x0400
++#define NV_PAUSEFRAME_RX_CAPABLE 0x0001
++#define NV_PAUSEFRAME_TX_CAPABLE 0x0002
++#define NV_PAUSEFRAME_RX_ENABLE 0x0004
++#define NV_PAUSEFRAME_TX_ENABLE 0x0008
++#define NV_PAUSEFRAME_RX_REQ 0x0010
++#define NV_PAUSEFRAME_TX_REQ 0x0020
++#define NV_PAUSEFRAME_AUTONEG 0x0040
++
++/* MSI/MSI-X defines */
++#define NV_MSI_X_MAX_VECTORS 8
++#define NV_MSI_X_VECTORS_MASK 0x000f
++#define NV_MSI_CAPABLE 0x0010
++#define NV_MSI_X_CAPABLE 0x0020
++#define NV_MSI_ENABLED 0x0040
++#define NV_MSI_X_ENABLED 0x0080
++
++#define NV_MSI_X_VECTOR_ALL 0x0
<<Diff was trimmed, longer than 597 lines>>
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