Author: hawk Date: Thu Mar 27 14:21:11 2008 GMT
Module: SOURCES Tag: Titanium
---- Log message:
- updated to v10.50.1.3
---- Files affected:
SOURCES:
linux-2.6.22-sk98lin.patch (1.1.2.1 -> 1.1.2.2)
---- Diffs:
================================================================
Index: SOURCES/linux-2.6.22-sk98lin.patch
diff -u SOURCES/linux-2.6.22-sk98lin.patch:1.1.2.1
SOURCES/linux-2.6.22-sk98lin.patch:1.1.2.2
--- SOURCES/linux-2.6.22-sk98lin.patch:1.1.2.1 Sun Nov 11 00:02:38 2007
+++ SOURCES/linux-2.6.22-sk98lin.patch Thu Mar 27 15:21:05 2008
@@ -1,6 +1,6 @@
diff -ruN linux/drivers/net/sk98lin/h/lm80.h
linux-new/drivers/net/sk98lin/h/lm80.h
--- linux/drivers/net/sk98lin/h/lm80.h 2007-07-09 01:32:17.000000000 +0200
-+++ linux-new/drivers/net/sk98lin/h/lm80.h 2007-10-19 15:05:21.000000000
+0200
++++ linux-new/drivers/net/sk98lin/h/lm80.h 2007-10-22 15:56:53.000000000
+0200
@@ -2,8 +2,8 @@
*
* Name: lm80.h
@@ -30,8 +30,8 @@
diff -ruN linux/drivers/net/sk98lin/h/mvyexhw.h
linux-new/drivers/net/sk98lin/h/mvyexhw.h
--- linux/drivers/net/sk98lin/h/mvyexhw.h 1970-01-01 01:00:00.000000000
+0100
-+++ linux-new/drivers/net/sk98lin/h/mvyexhw.h 2007-10-19 15:05:22.000000000
+0200
-@@ -0,0 +1,5050 @@
++++ linux-new/drivers/net/sk98lin/h/mvyexhw.h 2007-10-22 15:56:53.000000000
+0200
+@@ -0,0 +1,6022 @@
+/******************************************************************************
+ *
+ * Name: mvyexhw.h
@@ -230,6 +230,15 @@
+#define VPD_CTRL 0x00B8
/* 32 bit EEPROM and OTP
+
* Control Register
+
*/
++ /* Yukon-Supreme */
++#define FLASH_LDR_CTRL 0x00A4 /* 32
bit Flash Loader */
++ /* Yukon-Supreme */
++#define LD_STATUS_0 0x00A8
/* 32 bit LOADER STATUS */
++ /* Yukon-Supreme */
++#define VPD_FLASH_CTRL 0x00B8 /* 32
bit EEPROM and Flash
++
* Control Register
++
*/
++
+ /* Yukon-FE+ */
+#define OTP_MEM_CTRL_3 0x00BC /* 32
bit LDO Control Register */
+#define PCIE_CAP_ID 0x00C0
/* 8 bit PE Capability ID
@@ -289,7 +298,8 @@
+
* Capabilities and
+
* Control Register
+
*/
-+#define PCIE_HDRLOG 0x011C
/* 13 bit Header Log Registers */
++#define PCIE_HDRLOG_RNG_LO 0x011C /*
Header Log Registers Start */
++#define PCIE_HDRLOG_RNG_HI 0x0128 /*
Header Log Registers End */
+#define PCIE_DEVSERNUMCAP 0x0130 /* 32
bit Device Serial
+
* Number Enhanced
+
* Capability Header
@@ -313,7 +323,7 @@
+#define PCIE_PWRBDGT_DATA 0x0148 /* 32
bit Power Budgeting
+
* Data Register
+
*/
-+#define PCIE_PWRBDGT_CAP 0x014c /* 32
bit Power Budgeting
++#define PCIE_PWRBDGT_CAP 0x014C /* 32
bit Power Budgeting
+
* Capability
+
* Register
+
*/
@@ -352,11 +362,11 @@
+ */
+/* PCI_VEN_ID 0x0000 Vendor
ID Register */
+#define PCI_VEN_ID_MSK SHIFT0(0xffffU) /* Vendor ID */
-+#define PCI_VEN_ID_BASE BIT_0S
++#define PCI_VEN_ID_BASE 0
+
+/* PCI_DEV_ID 0x0002 Device
ID Register */
+#define PCI_DEV_ID_MSK SHIFT0(0xffffU) /* Device ID */
-+#define PCI_DEV_ID_BASE BIT_0S
++#define PCI_DEV_ID_BASE 0
+
+/* PCI_CMD 0x0004 Command
Register */
+/* Bit(s) PCI_CMD_RSRV_15_11 reserved */
@@ -384,21 +394,21 @@
+
+/* PCI_REV_ID 0x0008
Revision ID Register */
+#define PCI_REV_ID_MSK SHIFT0(0xffU) /* Revision ID */
-+#define PCI_REV_ID_BASE BIT_0S
++#define PCI_REV_ID_BASE 0
+
+/* PCI_PIF 0x0009
Programming Interface Register,
+ *
Lower Byte
+ */
-+#define PCI_PIF_MSK SHIFT0(0xffU) /* Prog IF */
-+#define PCI_PIF_BASE BIT_0S
++#define PCI_PIF_MSK SHIFT0(0xffU) /* Prog
Interface */
++#define PCI_PIF_BASE 0
+
+/* PCI_SCC 0x000A
Sub-Class Register, Middle Byte */
+#define PCI_SCC_MSK SHIFT0(0xffU) /* Sub Class */
-+#define PCI_SCC_BASE BIT_0S
++#define PCI_SCC_BASE 0
+
+/* PCI_BCC 0x000B
Base-Class Register, Upper Byte */
+#define PCI_BCC_MSK SHIFT0(0xffU) /* Base Class */
-+#define PCI_BCC_BASE BIT_0S
++#define PCI_BCC_BASE 0
+
+/* PCI_CLS 0x000C Cache
Line Size Register */
+/* Bit(s) PCI_CLS_RSRV_7_0 reserved */
@@ -490,7 +500,8 @@
+#define PCI_OUR1_ENEPROM BIT_22
/* En Eprom */
+#define PCI_OUR1_PAGE_SIZ_MSK SHIFT20(0x3) /*
Pagesize<1:0> */
+#define PCI_OUR1_PAGE_SIZ_BASE 20
-+/* Bit(s) PCI_OUR1_RSRV_19 reserved */
++ /* Yukon-Supreme */
++#define PCI_OUR1_ROM_SRC_SEL BIT_19
/* ROM Source Select */
+#define PCI_OUR1_PAGE_SEL_MSK SHIFT16(0x7) /* Page
Reg<2:0> */
+#define PCI_OUR1_PAGE_SEL_BASE 16
+#define PCI_OUR1_DBG_PEX_PME BIT_15
/* DEBUG_PEX_PME */
@@ -578,15 +589,16 @@
+#define PCI_VPD_DATA_BASE 0
+
+/* PCI_LDR_CTRL 0x0058 TWSI EEPROM
Loader Control Register */
-+#define PCI_LDR_CTRL_FLAG BIT_31
/* Flag */
-+#define PCI_LDR_CTRL_ADDR_MSK SHIFT16(0x7fff) /* TWSI EEPROM
loader Address */
-+#define PCI_LDR_CTRL_ADDR_BASE 16
-+/* EEPROM loader start Address for PCI loader */
-+#define PCI_LDR_CTRL_ADDR_PCI SHIFT8(0xff)
-+#define PCI_LDR_CTRL_ADDR_PCIB 8
++#define PCI_LDR_CTRL_FLAG BIT_31
/* Flag */
++/* TWSI EEPROM loader Address */
++#define PCI_LDR_CTRL_ADDR_TWSI_MSK SHIFT16(0x7fff)
++#define PCI_LDR_CTRL_ADDR_TWSI_BASE 16
++/* EEPROM loader start Address for PCI LOADER */
++#define PCI_LDR_CTRL_ADDR_PCI_MSK SHIFT8(0xff)
++#define PCI_LDR_CTRL_ADDR_PCI_BASE 8
+/* EEPROM loader start Address for PIG */
-+#define PCI_LDR_CTRL_ADDR_PIG SHIFT0(0xff)
-+#define PCI_LDR_CTRL_ADDR_PIGB 0
++#define PCI_LDR_CTRL_ADDR_PIG_MSK SHIFT0(0xff)
++#define PCI_LDR_CTRL_ADDR_PIG_BASE 0
+
+/* PCI_MSI_CAP_ID 0x005C MSI Capability
ID Register (MSI
+ *
Cap ID)
@@ -651,53 +663,60 @@
+/* Bit(s) PCIE_OUR_STAT_RSRV_15_0 reserved */
+
+/* PCIE_OUR3 0x0080 Our
Register 3 */
-+/* Mask L0 condition */
++/* Mask L0 Condition */
+#define PCIE_OUR3_MASK_L0_COMMA BIT_31
-+/* Mask L0s condition */
++/* Mask L0s Condition */
+#define PCIE_OUR3_MASK_L0S_COMMA BIT_30
+/* Select MACSec clock */
+#define PCIE_OUR3_MACSEC_CLK_SEL BIT_29
+/* Bit(s) PCIE_OUR3_RSRV_27_20 reserved */
-+/* Select MAC RX clock for TX */
-+#define PCIE_OUR3_CLK_RX_TO_TX BIT_28
-+/* disable clk_clk for MAC and PHY */
++/* Select MAC RX Clock for TX */
++#define PCIE_OUR3_CLK_RX_TO_TX BIT_28
++/* Disable Free Running Clock for GMAC and WOL */
++#define PCIE_OUR3_DIS_CLK_WOL_GMAC BIT_27
/* Yukon-Supreme */
++/* Bit(s) PCIE_OUR3_RSRV_26_21 reserved */
++/* Disable clk_clk for ASF Flash */
++#define PCIE_OUR3_CLK_FLASH_DIS BIT_20
/* Yukon-Supreme */
++/* Disable clk_clk for USB */
++#define PCIE_OUR3_CLK_USB_DIS BIT_19
/* Yukon-Supreme */
++/* Disable clk_clk for USB */
+#define PCIE_OUR3_CLK_PHY_DIS BIT_19
+#define PCIE_OUR3_CLK_ASF_REGS_DIS BIT_18
/* disable clk_asf */
+/* disable clk_macsec */
+#define PCIE_OUR3_CLK_MACSEC_REGS_DIS BIT_17
-+/* disable clk_pci_regs_d0 */
++/* Disable clk_pci_regs_d0 */
+#define PCIE_OUR3_CLK_PCI_REGS_DIS BIT_16
-+/* disable clk_core_ytb_arb */
++/* Disable clk_core_ytb_arb */
+#define PCIE_OUR3_CLK_CORE_YTB_ARB_DIS BIT_15
-+/* disable clk_mac_lnk1_d3 */
++/* Disable clk_mac_lnk1_d3 */
+#define PCIE_OUR3_CLK_MAC_LNK1_D3_DIS BIT_14
-+/* disable clk_core_lnk1_d0 */
++/* Disable clk_core_lnk1_d0 */
+#define PCIE_OUR3_CLK_CORE_LNK1_D0_DIS BIT_13
-+/* disable clk_mac_lnk1_d0 */
++/* Disable clk_mac_lnk1_d0 */
+#define PCIE_OUR3_CLK_MAC_LNK1_D0_DIS BIT_12
-+/* disable clk_core_lnk1_d3 */
++/* Disable clk_core_lnk1_d3 */
+#define PCIE_OUR3_CLK_CORE_LNK1_D3_DIS BIT_11
-+/* disable clk_pci_master_arb */
++/* Disable clk_pci_master_arb */
+#define PCIE_OUR3_CLK_PCI_MST_ARB_DIS BIT_10
-+/* disable clk_core_regs_d3 */
++/* Disable clk_core_regs_d3 */
+#define PCIE_OUR3_CLK_CORE_REGS_D3_DIS BIT_9
-+/* disable clk_pci_regs_d3 */
++/* Disable clk_pci_regs_d3 */
+#define PCIE_OUR3_CLK_PCI_REGS_D3_DIS BIT_8
-+/* disable clk_ref_lnk1_gmac */
++/* Disable clk_ref_lnk1_gmac */
+#define PCIE_OUR3_CLK_REF_LNK1_GMAC_DIS BIT_7
-+/* disable clk_core_lnk1_gmac */
++/* Disable clk_core_lnk1_gmac */
+#define PCIE_OUR3_CLK_CORE_LNK1_GMAC_DIS BIT_6
-+/* disable clk_pci_common */
++/* Disable clk_pci_common */
+#define PCIE_OUR3_CLK_PCI_COM_DIS BIT_5
-+/* disable clk_core_common */
++/* Disable clk_core_common */
+#define PCIE_OUR3_CLK_CORE_COM_DIS BIT_4
-+/* disable clk_pci_lnk1_bmu */
++/* Disable clk_pci_lnk1_bmu */
+#define PCIE_OUR3_CLK_PCI_LNK1_BMU_DIS BIT_3
-+/* disable clk_core_lnk1_bmu */
++/* Disable clk_core_lnk1_bmu */
+#define PCIE_OUR3_CLK_CORE_LNK1_BMU_DIS BIT_2
-+/* disable pci_clk_biu */
++/* Disable pci_clk_biu */
+#define PCIE_OUR3_PCI_CLK_BIU_DIS BIT_1
-+/* disable clk_core_biu */
++/* Disable clk_core_biu */
+#define PCIE_OUR3_CLK_CORE_BIU_DIS BIT_0
+
+#define PCIE_OUR3_WOL_D3_COLD_SETTING \
@@ -747,13 +766,6 @@
+/* Enable Gate Root Core Clock */
+#define PCIE_OUR4_GATE_ROOT_CORE_CLK_ENA BIT_0
+
-+#if 0
-+#define PCIE_OUR4_WOL_D3_COLD_SETTING \
-+ ( PCIE_OUR4_GATE_ROOT_CORE_CLK_ENA | \
-+ PCIE_OUR4_GATE_PEXUNIT_CLK_ENA | \
-+ PCIE_OUR4_TIM_VAL_MSK )
-+#endif
-+
+/* PCIE_OUR5 0x0088 Our
Register 5 */
+/* Divide Core Clock Enable */
+#define PCIE_OUR5_DIV_CORE_CLK_ENA BIT_31
@@ -811,21 +823,6 @@
+#define PCIE_OUR5_PCIE_RX_ELEC_IDLE BIT_1
+#define PCIE_OUR5_GPHY_LNK_DOWN BIT_0
/* GPHY Link Down */
+
-+#if 0
-+#define PCIE_OUR5_WOL_D3_COLD_SETTING \
-+ ( PCIE_OUR5_PME_DEASS | \
-+ PCIE_OUR5_CLKRUN_NOT_REQ | \
-+ PCIE_OUR5_MAIN_PWR_NOT_AVL | \
-+ PCIE_OUR5_INTERNAL_FIFO_EMPTY | \
-+ PCIE_OUR5_GPHY_NOT_RX_PKT | \
-+ PCIE_OUR5_PME_ASS | \
-+ PCIE_OUR5_CLKRUN_REQ | \
-+ PCIE_OUR5_MAIN_PWR_AVL | \
-+ PCIE_OUR5_INT_FIFO_NOT_EMPTY | \
-+ PCIE_OUR5_GPHY_RX_PKT | \
-+ PCIE_OUR5_DIV_CORE_CLK_ENA )
-+#endif
-+
+/* PCIE_ER_MASK 0x008C Error Reporting
Mask Register */
+/* Enable the Device Feature Set SERR */
+#define PCIE_ER_MASK_DEV_FEAT_SET_SERR_ENA BIT_31
@@ -894,14 +891,24 @@
+#define CONFIG_REG0_WTC_MSK
SHIFT16(0xff) /* WTC */
+#define CONFIG_REG0_WTC_BASE
16
+/* Disable PCIe reset extend after Lom_disable */
-+#define CONFIG_REG0_PCIRST_LOM
BIT_15
-+/* Bit(s) CONFIG_REG0_RSRV_14_13 reserved */
++#define CONFIG_REG0_PCIRST_LOM
BIT_15
++/* Enable CPU FINT to clock gating */
++#define CONFIG_REG0_CLK_GATE_CPU_INT BIT_14
/* Yukon-Supreme */
++/* Enable clock free running for ASF subsystem */
++#define CONFIG_REG0_CLK_RUN_ASF
BIT_13 /* Yukon-Supreme */
++/* Enable clock free running for Flash subsystem */
++#define CONFIG_REG0_CLK_RUN_FLASH
BIT_12 /* Yukon-Supreme */
++/* Random Generator Speed Control */
+#define CONFIG_REG0_OSC_PU
BIT_12 /* OSC Power Up */
+/* OSC Speed Control */
+#define CONFIG_REG0_OSC_SPEED_CTRL_MSK
SHIFT9(0x7)
+#define CONFIG_REG0_OSC_SPEED_CTRL_BASE BIT_9
+#define CONFIG_REG0_OSC_OUT
BIT_8 /* OSC output */
-+/* Bit(s) CONFIG_REG0_RSRV_7_5 reserved */
++/* Random Generator output */
++#define CONFIG_REG0_RNDG_OUT
BIT_8
++/* Bit(s) CONFIG_REG0_RSRV_7 reserved */
++#define CONFIG_REG0_YTB_ARB_MODE_MSK
SHIFT5(0x3) /* YTB ARB Mode */
++#define CONFIG_REG0_YTB_ARB_MODE_BASE 5
+/* Disable GPHY reset on Lom_disable mode */
+#define CONFIG_REG0_GPHY_RST_LOMDISABLE BIT_4
+/* Disable GPHY DPLL reset on Lom_disable mode */
@@ -914,7 +921,15 @@
+#define CONFIG_REG0_CPU_LOCK_VPD
BIT_0
+
+/* CONFIG_REG1 0x0094 Config
Register 1 */
-+/* Bit(s) CONFIG_REG1_RSRV_31_25 reserved */
++/* Testmode enable */
++#define CONFIG_REG1_EN_TESTMODE
BIT_31
++#define CONFIG_REG1_TESTMODE_SEL_MSK
SHIFT28(0x7) /* Testmode Sel */
++#define CONFIG_REG1_TESTMODE_SEL_BASE 28
++/* Bit(s) CONFIG_REG1_RSRV_27 reserved */
++/* USB_RESUME_RELEASE */
++#define CONFIG_REG1_USB_RESUME_RELEASE_CLK BIT_26
++/* USB_RESUME_GATE */
++#define CONFIG_REG1_USB_RESUME_GATE_CLK BIT_25
+/* Disable Release event in CFG0x84 during PCIE reset asserted */
+#define CONFIG_REG1_DIS_CFG84_EVENT
BIT_24
+/* EPROM Loader Not Finished */
@@ -934,12 +949,12 @@
+/* Bit(s) CONFIG_REG1_RSRV_15_9 reserved */
+/* Enable core level Config loader done for gated clock */
+#define CONFIG_REG1_EN_CFG_LOAD_DONE BIT_8
-+/* Enable PCIe Header Log Fix1 */
-+#define CONFIG_REG1_ENA_PCIE_HDRLOG_FIX1 BIT_7
++/* Enable PCIe Header Log Fix */
++#define CONFIG_REG1_ENA_PCIE_HDRLOG_FIX BIT_7
+/* Enable PCIe CRS Fix */
+#define CONFIG_REG1_EN_PCIE_CRS_FIX
BIT_6
-+/* Disable PCIe Header Log Fix0 */
-+#define CONFIG_REG1_DIS_PCIE_HDRLOG_FIX0 BIT_5
++/* FIFO Clock Duty Cycle Control */
++#define CONFIG_REG1_FIFO_CLK_DUTY_CYC_CTRL BIT_5
+/* Disable pexunit Synchronization Fix */
+#define CONFIG_REG1_DIS_PEX_SYNC_FIX BIT_4
+/* Enable CPU reset gated by YTB cmd */
@@ -998,6 +1013,21 @@
+#define VPD_CTRL_ADD_OTP_EN BIT_1
/* OTP_EN */
+#define VPD_CTRL_ADD_VPD_SEL BIT_0
/* VPD_SEL */
+
++/* Yukon-Supreme */
++/* FLASH_LDR_CTRL 0x00A4 Flash Loader
Control Register */
++#define FLASH_LDR_CTRL_OTP_FLAG
BIT_31 /* Flag */
++#define FLASH_LDR_CTRL_FLASH_REGION
BIT_30 /* Flash region */
++/* Flash loader Address */
++#define FLASH_LDR_CTRL_FLASH_ADDR_MSK
SHIFT16(0x3fff)
++#define FLASH_LDR_CTRL_FLASH_ADDR_BASE 16
++/* Flash start Address for PCI Loader */
++#define FLASH_LDR_CTRL_FLASH_LOADER_PCI_MSK
SHIFT8(0xff)
++#define FLASH_LDR_CTRL_FLASH_LOADER_PCI_BASE 8
++/* Flash start Address for PIG */
++#define FLASH_LDR_CTRL_FLASH_LOADER_PIG_MSK
SHIFT0(0xff)
++#define FLASH_LDR_CTRL_FLASH_LOADER_PIG_BASE 0
++
++/* Yukon-Fe+ */
+/* OTP_LDR_CTRL 0x00A4 OTP Loader
Control Register */
+#define OTP_LDR_CTRL_OTP_FLAG
BIT_31 /* Flag */
+#define OTP_LDR_CTRL_OTP_ADDR_MSK
SHIFT16(0x7fff) /* OTP Address */
@@ -1015,6 +1045,13 @@
+#define OTP_LDR_CTRL_OTP_ST_ADD_MSK
SHIFT0(0xff)
+#define OTP_LDR_CTRL_OTP_ST_ADD_BASE 0
+
++/* Yukon-Supreme */
++/* LD_STATUS_0 0x00A8 LOADER
STATUS */
++/* Flash AHB timeout */
++#define LD_STATUS_0_FLASH_LOADER_TIMEOUT BIT_31
++/* Bit(s) LD_STATUS_0_RSRV_29_0 reserved */
++
++/* Yukon-Fe+ */
+/* OTP_MEM_CTRL_0 0x00A8 OTP Memory
Control Register 0 */
+#define OTP_MEM_CTRL_0_CE2RD_SU_TIME_MSK SHIFT24(0xff)
/* CERD setup time */
+#define OTP_MEM_CTRL_0_CE2RD_SU_TIME_BASE 24
@@ -1073,6 +1110,41 @@
+#define OTP_MEM_ST_0_OTP_DOUT_PIN BIT_23
+/* Bit(s) OTP_MEM_ST_0_RSRV_22_0 reserved */
+
++/* Yukon-Supreme */
++/* VPD_FLASH_CTRL 0x00B8 EEPROM and
Flash Control Register */
++/* Disable MDIO to YTB Bus Read/Write */
++#define VPD_FLASH_CTRL_MDIO2YTB_DIS
BIT_31
++/* Software Reset MDIO to YTB Bus */
++#define VPD_FLASH_CTRL_MDIO2YTB_SWRST BIT_30
++/* Bit(s) VPD_FLASH_CTRL_RSRV_29_28 reserved */
++/* Flash Loader AHB Request Timeout Disable */
++#define VPD_FLASH_CTRL_FLASH_AHB_TIMEOUT_DIS BIT_27
++/* TWSI serial interface timeout disable */
++#define VPD_FLASH_CTRL_TWSI_IF_TIMEOUT_DIS BIT_26
++/* Bit(s) VPD_FLASH_CTRL_RSRV_25_24 reserved */
++/* Flash loader AHB request timeout value */
++#define VPD_FLASH_CTRL_FLASH_AHB_TIMEOUT_MSK SHIFT21(0x7)
++#define VPD_FLASH_CTRL_FLASH_AHB_TIMEOUT_BASE 21
++/* Bit(s) VPD_FLASH_CTRL_RSRV_20 reserved */
++/* TWSI serial interface timeout value */
++#define VPD_FLASH_CTRL_TWSI_IF_TIMEOUT_MSK
SHIFT17(0x7)
++#define VPD_FLASH_CTRL_TWSI_IF_TIMEOUT_BASE 17
++/* Bit(s) VPD_FLASH_CTRL_RSRV_16 reserved */
++/* EEPROM loader timeout disable */
++#define VPD_FLASH_CTRL_EEPROM_TMOUT_DIS BIT_15
++/* Flash Loader timeout Disable */
++#define VPD_FLASH_CTRL_FLASH_TMOUT_DIS BIT_14
++/* EEPROM loader timeout val */
++#define VPD_FLASH_CTRL_EEPROM_TMOUT_VALUE_MSK SHIFT12(0x3)
++#define VPD_FLASH_CTRL_EEPROM_TMOUT_VALUE_BASE 12
++/* Flash Loader timeout val */
++#define VPD_FLASH_CTRL_FLASH_TMOUT_VALUE_MSK SHIFT10(0x3)
++#define VPD_FLASH_CTRL_FLASH_TMOUT_VALUE_BASE 10
++/* EEPROM speed select */
++#define VPD_FLASH_CTRL_SPEED_SELECT_MSK
SHIFT0(0x3ff)
++#define VPD_FLASH_CTRL_SPEED_SELECT_BASE 0
++
++/* Yukon-Fe+ */
+/* VPD_CTRL 0x00B8 EEPROM
and OTP Control Register */
+/* mdio to ytb bus IF disable */
+#define VPD_CTRL_MDIO2YTB_DIS BIT_31
@@ -1093,8 +1165,7 @@
+#define VPD_CTRL_SPEED_SELECT_BASE 0
+
+/* OTP_MEM_CTRL_3 0x00BC LDO Control
Register */
-+//#define _MSK
SHIFT14(0x3ffff) /* RSVD */
-+//#define _BASE
14
++/* Bit(s) OTP_MEM_CTRL_3_RSRV_31_14 reserved */
+/* CLK generator filter bypass */
+#define OTP_MEM_CTRL_3_CLK_GEN_BYPASS BIT_13
+/* CLK generator soft reset */
@@ -1218,7 +1289,7 @@
+/* Enable Clock Power Management */
+#define PCIE_LNKCTRL_CLK_PM_ENA BIT_8S
+#define PCIE_LNKCTRL_EXTSYNC BIT_7S
/* Extended Sync */
-+/* Bit(s) PCIE_LNKCTRL_RSRV_ reserved */
++/* Bit(s) PCIE_LNKCTRL_RSRV_6 reserved */
+/* Bit(s) PCIE_LNKCTRL_RSRV_5_4 reserved */
+/* Read Completion Boundary (RCB) */
+#define PCIE_LNKCTRL_RCB_128B BIT_3S
@@ -1230,10 +1301,11 @@
+/* PCIE_LNKSTAT 0x00D2 Link Status
Register */
+/* Bit(s) PCIE_LNKSTAT_RSRV_15_14 reserved */
+/* Bit(s) PCIE_LNKSTAT_RSRV_13 reserved */
-+#define PCIE_LNKSTAT_SCLKCFG BIT_12S
/* Slot Clock Configuration */
-+#define PCIE_LNKSTAT_LNKTRAIN BIT_11S
/* Link Training */
-+#define PCIE_LNKSTAT_UNDEF BIT_10S
/* Undefined */
-+#define PCIE_LNKSTAT_NEGLNKWID_MSK SHIFT4(0x3fU) /*
Negotiated Link Width */
++/* Slot Clock Configuration */
++#define PCIE_LNKSTAT_SCLKCFG BIT_12S
++#define PCIE_LNKSTAT_LNKTRAIN BIT_11S
/* Link Training */
++#define PCIE_LNKSTAT_UNDEF BIT_10S
/* Undefined */
++/* Negotiated Link Width */
+#define PCIE_LNKSTAT_NEGLNKWID_MSK SHIFT4(0x3fU)
+#define PCIE_LNKSTAT_NEGLNKWID_BASE 4
+#define PCIE_LNKSTAT_LNKSPD_MSK SHIFT0(0xfU)
/* Link Speed */
@@ -1269,58 +1341,64 @@
+/* PCIE_UE_STAT 0x0104 Uncorrectable
Error Status Register */
+/* Bit(s) PCIE_UE_STAT_RSRV_31_21 reserved */
+/* Unsupported Request Error */
-+#define PCIE_UE_STAT_UR BIT_20
-+#define PCIE_UE_STAT_ECRCERR BIT_19
/* ECRC Error */
-+#define PCIE_UE_STAT_MTLP BIT_18
/* Malformed TLP */
-+#define PCIE_UE_STAT_RCVOVFL BIT_17
/* Receiver Overflow */
-+#define PCIE_UE_STAT_UNEXPCPL BIT_16
/* Unexpected Completion */
-+#define PCIE_UE_STAT_CPLABORT BIT_15
/* Completer Abort */
-+#define PCIE_UE_STAT_CPLTO BIT_14
/* Completion Timeout */
++#define PCIE_UE_STAT_UR BIT_20
++#define PCIE_UE_STAT_ECRCERR BIT_19
/* ECRC Error */
++#define PCIE_UE_STAT_MTLP BIT_18
/* Malformed TLP */
++#define PCIE_UE_STAT_RCVOVFL BIT_17
/* Receiver Overflow */
++/* Unexpected Completion */
++#define PCIE_UE_STAT_UNEXPCPL BIT_16
++#define PCIE_UE_STAT_CPLABORT BIT_15
/* Completer Abort */
++#define PCIE_UE_STAT_CPLTO BIT_14
/* Completion Timeout */
+/* Flow Control Protocol Error */
-+#define PCIE_UE_STAT_FCPROTERR BIT_13
-+#define PCIE_UE_STAT_PTLP BIT_12
/* Poisoned TLP */
++#define PCIE_UE_STAT_FCPROTERR BIT_13
++#define PCIE_UE_STAT_PTLP BIT_12
/* Poisoned TLP */
+/* Bit(s) PCIE_UE_STAT_RSRV_11_5 reserved */
-+#define PCIE_UE_STAT_DLPROTERR BIT_4
/* Data Link Protocol Error */
++/* Data Link Protocol Error */
++#define PCIE_UE_STAT_DLPROTERR BIT_4
+/* Bit(s) PCIE_UE_STAT_RSRV_3_1 reserved */
-+#define PCIE_UE_STAT_UNDEF BIT_0
/* Undefined */
++#define PCIE_UE_STAT_UNDEF BIT_0
/* Undefined */
+
+/* PCIE_UE_MASK 0x0108 Uncorrectable
Error Mask Register */
+/* Bit(s) PCIE_UE_MASK_RSRV_31_21 reserved */
+/* Unsupported Request Error */
-+#define PCIE_UE_MASK_UR BIT_20
-+#define PCIE_UE_MASK_ECRCERR BIT_19
/* ECRC Error */
-+#define PCIE_UE_MASK_MTLP BIT_18
/* Malformed TLP */
-+#define PCIE_UE_MASK_RCVOVFL BIT_17
/* Receiver Overflow */
-+#define PCIE_UE_MASK_UNEXPCPL BIT_16
/* Unexpected Completion */
-+#define PCIE_UE_MASK_CPLABRT BIT_15
/* Completer Abort */
-+#define PCIE_UE_MASK_CPLTO BIT_14
/* Completion Timeout */
++#define PCIE_UE_MASK_UR BIT_20
++#define PCIE_UE_MASK_ECRCERR BIT_19
/* ECRC Error */
++#define PCIE_UE_MASK_MTLP BIT_18
/* Malformed TLP */
++#define PCIE_UE_MASK_RCVOVFL BIT_17
/* Receiver Overflow */
++/* Unexpected Completion */
++#define PCIE_UE_MASK_UNEXPCPL BIT_16
++#define PCIE_UE_MASK_CPLABRT BIT_15
/* Completer Abort */
++#define PCIE_UE_MASK_CPLTO BIT_14
/* Completion Timeout */
+/* Flow Control Protocol Error */
-+#define PCIE_UE_MASK_FCPROTERR BIT_13
-+#define PCIE_UE_MASK_PTLP BIT_12
/* Poisoned TLP */
++#define PCIE_UE_MASK_FCPROTERR BIT_13
++#define PCIE_UE_MASK_PTLP BIT_12
/* Poisoned TLP */
+/* Bit(s) PCIE_UE_MASK_RSRV_11_5 reserved */
-+#define PCIE_UE_MASK_DLPROTERR BIT_4
/* Data Link Protocol Error */
++/* Data Link Protocol Error */
++#define PCIE_UE_MASK_DLPROTERR BIT_4
+/* Bit(s) PCIE_UE_MASK_RSRV_3_1 reserved */
-+#define PCIE_UE_MASK_UNDEF BIT_0
/* Undefined */
++#define PCIE_UE_MASK_UNDEF BIT_0
/* Undefined */
+
+/* PCIE_UE_SVRT 0x010C Uncorrectable
Error Severity
+ *
Register
+ */
+/* Bit(s) PCIE_UE_SVRT_RSRV_31_21 reserved */
+/* Unsupported Request Error */
-+#define PCIE_UE_SVRT_UR BIT_20
-+#define PCIE_UE_SVRT_ECRCERR BIT_19
/* ECRC Error Severity */
-+#define PCIE_UE_SVRT_MTLP BIT_18
/* Malformed TLP */
-+#define PCIE_UE_SVRT_RCVOVFL BIT_17
/* Receiver Overflow */
-+#define PCIE_UE_SVRT_UNEXPCPL BIT_16
/* Unexpected Completion */
-+#define PCIE_UE_SVRT_CPLABRT BIT_15
/* Completer Abort */
-+#define PCIE_UE_SVRT_CPLTO BIT_14
/* Completion Timeout */
++#define PCIE_UE_SVRT_UR BIT_20
++#define PCIE_UE_SVRT_ECRCERR BIT_19
/* ECRC Error Severity */
++#define PCIE_UE_SVRT_MTLP BIT_18
/* Malformed TLP */
++#define PCIE_UE_SVRT_RCVOVFL BIT_17
/* Receiver Overflow */
++/* Unexpected Completion */
++#define PCIE_UE_SVRT_UNEXPCPL BIT_16
++#define PCIE_UE_SVRT_CPLABRT BIT_15
/* Completer Abort */
++#define PCIE_UE_SVRT_CPLTO BIT_14
/* Completion Timeout */
+/* Flow Control Protocol Error */
-+#define PCIE_UE_SVRT_FCPROTERR BIT_13
-+#define PCIE_UE_SVRT_PTLP BIT_12
/* Poisoned TLP */
++#define PCIE_UE_SVRT_FCPROTERR BIT_13
++#define PCIE_UE_SVRT_PTLP BIT_12
/* Poisoned TLP */
+/* Bit(s) PCIE_UE_SVRT_RSRV_11_5 reserved */
-+#define PCIE_UE_SVRT_DLPROTERR BIT_4
/* Data Link Protocol Error */
++/* Data Link Protocol Error */
++#define PCIE_UE_SVRT_DLPROTERR BIT_4
+/* Bit(s) PCIE_UE_SVRT_RSRV_3_1 reserved */
-+#define PCIE_UE_SVRT_UNDEF BIT_0
/* Undefined */
++#define PCIE_UE_SVRT_UNDEF BIT_0
/* Undefined */
+
+/* PCIE_CA_STAT 0x0110 Correctable
Error Status Register */
+/* Bit(s) PCIE_CA_STAT_RSRV_31_14 reserved */
@@ -1426,7 +1504,7 @@
+#define PCIE_PWRBDGT_DATA_BASEPWR_MSK SHIFT0(0xff)
/* Base Power */
+#define PCIE_PWRBDGT_DATA_BASEPWR_BASE 0
+
-+/* PCIE_PWRBDGT_CAP 0x014c Power Budgeting
Capability Register */
++/* PCIE_PWRBDGT_CAP 0x014C Power Budgeting
Capability Register */
+/* Bit(s) PCIE_PWRBDGT_CAP_RSRV_31_1 reserved */
+#define PCIE_PWRBDGT_CAP_SYSALLOC BIT_0
/* System Allocated */
+
@@ -1541,6 +1619,7 @@
+ *
Register
+ */
+#define GLB_BWIN 0x0080 /* 32 bit Block
Window Register */
++
+#define L1_CFG_MADDR_HI 0x0100 /*32 bit Link1 MAC
Address Register High */
+#define M_CFG_MADDR_HI 0x0110 /*32 bit maintenance MAC
Address Register High */
+#define L1_CFG_MADDR_LO 0x0104 /*32 bit Link1 MAC
Address Register Low */
@@ -1585,7 +1664,10 @@
+#define RAM_DATA_LO 0x0184 /* 32 bit Data
Port/Lower Dword Register */
+#define RAM_DATA_HI 0x0188 /* 32 bit Data
Port/Upper Dword Register */
+#define ASF_TO 0x0190 /* 32 bit Timeout
Register */
++#define ASF_TO_4 0x0194 /* 32 bit Timeout
Register */
++#define ASF_SRAMTC 0x0198 /* 32 bit Timeout
Register */
+#define ASF_CTRL 0x01A0 /* 32 bit FIFO
Interface Control */
++
+#define RSS_KEY0 0x0220 /* 32 bit RSS Key
0 Register */
+#define RSS_KEY1 0x0224 /* 32 bit RSS Key
1 Register */
+#define RSS_KEY2 0x0228 /* 32 bit RSS Key
2 Register */
@@ -1597,6 +1679,15 @@
+#define RSS_KEY8 0x0240 /* 32 bit RSS Key
8 Register */
+#define RSS_KEY9 0x0244 /* 32 bit RSS Key
9 Register */
+#define RSS_CFG 0x0248 /* 32 bit RSS
Configuration Register */
++#define FCU_MEM_BASE_ADDR 0x0300 /* 32 bit FCU Memory Base
Address */
++#define FCU_REG_BASE_ADDR 0x0304 /* 32 bit FCU Register
Base Address */
++#define FCU_MEM_CTRL 0x0308 /* 32 bit FCU
Memory/Register Control */
++#define FCU_RD_DATA 0x030C /* 32 bit FCU
Memory/Register Read Data */
++#define FCU_WR_DATA 0x0310 /* 32 bit FCU
Memory/Register Write Data */
++#define FCU_IMEM_BASE_ADDR 0x0314 /* 32 bit FCU Information
Memory offset
++ *
Address
++ */
++#define FCU_ROM_BASE_ADDR 0x0318 /* 32 bit FCU ROM Base
Address */
+#define RBMU_DESCR 0x0400 /* 32 bit Current
Receive Descriptor
+ *
Register
+ */
@@ -1736,6 +1827,7 @@
+#define TPFU_FIFO_LEV 0x06FC /* 32 bit Transmit PFU
FIFO Shadow Level
+ *
Register
+ */
++
+#define RA_SADDR 0x0900 /* 32 bit ASF
Receive FIFO Start Address */
+#define RA_EADDR 0x0904 /* 32 bit ASF
Receive FIFO End Address */
+#define RA_WPTR 0x0908 /* 32 bit ASF
Receive FIFO Write Pointer */
@@ -1787,6 +1879,9 @@
+#define RXMF_RLEV 0x0C78 /* 32 bit Receive
MAC FIFO Read Level
+ *
Register
+ */
++#define RXMF_FCNT 0x0C7C /* 32 bit Receive
MAC FIFO Flush Counter
++ *
Register
++ */
+#define TXMF_EADDR 0x0D40 /* 32 bit
Transmit MAC FIFO End Address
+ *
Register
+ */
@@ -1837,6 +1932,7 @@
+#define CPU_WDOG 0x0E48 /* 32 bit
Watchdog Register */
+#define CPU_CNTR 0x0E4C /* 32 bit Counter
Register */
+#define CPU_TIM 0x0E50 /* 32 bit Timer
Compare Register */
++#define CPU_TIM_2 0x0E54 /* 32 bit Timer
Compare Register (Y-Supreme)*/
+#define CPU_AHB_ADDR 0x0E54 /* 32 bit CPU AHB Debug
Register */
+#define CPU_AHB_WDATA 0x0E58 /* 32 bit CPU AHB Debug
Register */
+#define CPU_AHB_RDATA 0x0E5C /* 32 bit CPU AHB Debug
Register */
<<Diff was trimmed, longer than 597 lines>>
---- CVS-web:
http://cvs.pld-linux.org/cgi-bin/cvsweb.cgi/SOURCES/linux-2.6.22-sk98lin.patch?r1=1.1.2.1&r2=1.1.2.2&f=u
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