Author: hawk Date: Fri Apr 25 13:27:33 2008 GMT Module: SOURCES Tag: Titanium ---- Log message: - vendor driver for Marvell Yukon gigabit adapters, v10.50.1.3
---- Files affected:
SOURCES:
linux-2.6.25-sk98lin.patch (NONE -> 1.1.2.1) (NEW)
---- Diffs:
================================================================
Index: SOURCES/linux-2.6.25-sk98lin.patch
diff -u /dev/null SOURCES/linux-2.6.25-sk98lin.patch:1.1.2.1
--- /dev/null Fri Apr 25 15:27:33 2008
+++ SOURCES/linux-2.6.25-sk98lin.patch Fri Apr 25 15:27:27 2008
@@ -0,0 +1,71358 @@
+diff -ruN linux/drivers/net/sk98lin/h/lm80.h
linux-new/drivers/net/sk98lin/h/lm80.h
+--- linux/drivers/net/sk98lin/h/lm80.h 2008-04-17 04:49:44.000000000 +0200
++++ linux-new/drivers/net/sk98lin/h/lm80.h 2007-10-22 15:56:53.000000000
+0200
+@@ -2,8 +2,8 @@
+ *
+ * Name: lm80.h
+ * Project: Gigabit Ethernet Adapters, Common Modules
+- * Version: $Revision$
+- * Date: $Date$
++ * Version: $Revision$
++ * Date: $Date$
+ * Purpose: Contains all defines for the LM80 Chip
+ * (National Semiconductor).
+ *
+@@ -11,6 +11,7 @@
+
+
/******************************************************************************
+ *
++ * LICENSE:
+ * (C)Copyright 1998-2002 SysKonnect.
+ * (C)Copyright 2002-2003 Marvell.
+ *
+@@ -20,6 +21,7 @@
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
++ * /LICENSE
+ *
+
******************************************************************************/
+
+diff -ruN linux/drivers/net/sk98lin/h/mvyexhw.h
linux-new/drivers/net/sk98lin/h/mvyexhw.h
+--- linux/drivers/net/sk98lin/h/mvyexhw.h 1970-01-01 01:00:00.000000000
+0100
++++ linux-new/drivers/net/sk98lin/h/mvyexhw.h 2007-10-22 15:56:53.000000000
+0200
+@@ -0,0 +1,6022 @@
++/******************************************************************************
++ *
++ * Name: mvyexhw.h
++ * Project: Yukon Extreme, Common Modules
++ * Version: $Revision$
++ * Date: $Date$
++ * Purpose: Defines and Macros for the Yukon Extreme Gigabit Ethernet
Adapters
++ *
++
******************************************************************************/
++
++/******************************************************************************
++ *
++ * LICENSE:
++ * (C)Copyright 2005-2007 Marvell.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ * The information in this file is provided "AS IS" without warranty.
++ * /LICENSE
++ *
++
******************************************************************************/
++
++/******************************************************************************
++ *
++ * This file was automatically generated by reg.pl (Rev. 1.55) using
++ * Yukon_Extreme_Registers_Config.csv
++ * Yukon_Extreme_Registers_Control.csv
++ * Yukon_Extreme_Registers_GMAC.csv
++ *
++
******************************************************************************/
++
++#ifndef __INC_MVYEXHW_H
++#define __INC_MVYEXHW_H
++
++#define PCI_VEN_ID 0x0000
/* 16 bit Vendor ID Register */
++#define PCI_DEV_ID 0x0002
/* 16 bit Device ID Register */
++#define PCI_CMD 0x0004
/* 16 bit Command Register */
++#define PCI_STAT 0x0006
/* 16 bit Status Register */
++//#define PCI_REV_ID 0x0008
/* 8 bit Revision ID Register */
++#define PCI_PIF 0x0009
/* 8 bit Programming
++
* Interface
++
* Register, Lower
++
* Byte
++
*/
++#define PCI_SCC 0x000A
/* 8 bit Sub-Class Register,
++
* Middle Byte
++
*/
++#define PCI_BCC 0x000B
/* 8 bit Base-Class
++
* Register, Upper
++
* Byte
++
*/
++#define PCI_CLS 0x000C
/* 8 bit Cache Line Size
++
* Register
++
*/
++//#define PCI_LAT_TIM 0x000D
/* 8 bit Latency Timer
++//
* Register
++//
*/
++#define PCI_HDRTYP 0x000E
/* 8 bit Header Type Register */
++//#define PCI_BIST 0x000F
/* 8 bit Built-in Self Test
++//
* (BIST) Register
++//
*/
++#define PCI_BAR1_LO 0x0010
/* 32 bit Base Address
++
* Register (1st),
++
* Lower Address
++
*/
++#define PCI_BAR1_HI 0x0014
/* 32 bit Base Address
++
* Register (1st),
++
* Upper Address
++
*/
++#define PCI_BAR2 0x0018
/* 32 bit Base Address
++
* Register (2nd)
++
*/
++#define PCI_SSVEN_ID 0x002C /* 16
bit Subsystem Vendor ID
++
* Register
++
*/
++#define PCI_SSDEV_ID 0x002E /* 16
bit Subsystem ID
++
* Register
++
*/
++#define PCI_ERBAR 0x0030
/* 32 bit Expansion Rom Base
++
* Address Register
++
*/
++#define PCI_NCAP_PTR 0x0034 /* 8
bit New Capabilities
++
* Pointer (New Cap
++
* Ptr) Register
++
*/
++#define PCI_INT_LINE 0x003C /* 8
bit Interrupt Line
++
* Register
++
*/
++#define PCI_INT_PIN 0x003D
/* 8 bit Interrupt Pin
++
* Register
++
*/
++//#define PCI_MIN_GNT 0x003E
/* 8 bit Min_Gnt Register */
++//#define PCI_MAX_LAT 0x003F
/* 8 bit Max_Lat Register */
++#define PCI_OUR1 0x0040
/* 32 bit Our Register 1 */
++#define PCI_OUR2 0x0044
/* 32 bit Our Register 2 */
++//#define PCI_PM_CAP_ID 0x0048 /* 8
bit Power Management
++//
* Capability ID
++//
* Register (PM Cap
++//
* ID)
++//
*/
++#define PCI_PM_NXT_PTR 0x0049 /* 8
bit Power Management
++
* Next Item Pointer
++
* Register
++
*/
++#define PCI_PM_CAP 0x004A
/* 16 bit Power Management
++
* Capabilities
++
* Register
++
*/
++#define PCI_PM_CSR 0x004C
/* 16 bit Power Management
++
* Control/Status
++
* Register
++
*/
++#define PCI_PM_DATA 0x004F
/* 8 bit Power Management
++
* Data Register
++
*/
++//#define PCI_VPD_CAP_ID 0x0050 /* 8
bit VPD Capability ID
++//
* Register (VPD Cap
++//
* ID)
++//
*/
++#define PCI_VPD_NPTR 0x0051 /* 8
bit VPD Next Item
++
* Pointer Register
++
*/
++#ifdef XXX /* Naming Conflict with Linux */
++#define PCI_VPD_ADDR 0x0052 /* 16
bit VPD Address Register */
++#define PCI_VPD_DATA 0x0054 /* 32
bit VPD Data Register */
++#endif /* XXX */
++#define PCI_LDR_CTRL 0x0058 /* 32
bit TWSI EEPROM Loader
++
* Control Register
++
*/
++//#define PCI_MSI_CAP_ID 0x005C /* 8
bit MSI Capability ID
++//
* Register (MSI Cap
++//
* ID)
++//
*/
++#define PCI_MSI_NPTR 0x005D /* 8
bit MSI Next Item
++
* Pointer Register
++
*/
++//#define PCI_MSI_CTRL 0x005E /* 16
bit MSI Message Control
++//
* Register
++//
*/
++#define PCI_MSI_ADDR_LO 0x0060 /* 32
bit MSI Message Address
++
* Register, Lower
++
* Address
++
*/
++#define PCI_MSI_ADDR_HI 0x0064 /* 32
bit MSI Message Address
++
* Register, Upper
++
* Address
++
*/
++//#define PCI_MSI_DATA 0x0068 /* 32
bit MSI Message Data
++//
* Register
++//
*/
++#define PCIE_STAT 0x0070
/* 32 bit PCI Express Status
++
* Register
++
*/
++#define PCIE_OUR_STAT 0x007C /* 32
bit Our Status Register */
++#define PCIE_OUR3 0x0080
/* 32 bit Our Register 3 */
++#define PCIE_OUR4 0x0084
/* 32 bit Our Register 4 */
++#define PCIE_OUR5 0x0088
/* 32 bit Our Register 5 */
++#define PCIE_ER_MASK 0x008C /* 32
bit Error Reporting
++
* Mask Register
++
*/
++#define CONFIG_REG0 0x0090
/* 32 bit Config Register 0 */
++#define CONFIG_REG1 0x0094
/* 32 bit Config Register 1 */
++#define PSM_CONFIG_REG0 0x0098 /* 32
bit PSM Config Register
++
* 0
++
*/
++#define PSM_CONFIG_REG1 0x009C /* 32
bit PSM Config Register
++
* 1
++
*/
++ /* Yukon-FE+ */
++#define VPD_CTRL_ADD 0x00A0 /* 32
bit VPD Start End
++
* Address
++
*/
++ /* Yukon-FE+ */
++#define OTP_LDR_CTRL 0x00A4 /* 32
bit OTP Loader Control
++
* Register
++
*/
++ /* Yukon-FE+ */
++#define OTP_MEM_CTRL_0 0x00A8 /* 32
bit OTP Memory Control
++
* Register 0
++
*/
++ /* Yukon-FE+ */
++#define OTP_MEM_CTRL_1 0x00AC /* 32
bit OTP Memory Control
++
* Register 1
++
*/
++ /* Yukon-FE+ */
++#define OTP_MEM_CTRL_2 0x00B0 /* 32
bit OTP Memory Control
++
* Register 2
++
*/
++ /* Yukon-FE+ */
++#define OTP_MEM_ST_0 0x00B4 /* 32
bit OTP Memory Status
++
* Register 0
++
*/
++ /* Yukon-FE+ */
++#define VPD_CTRL 0x00B8
/* 32 bit EEPROM and OTP
++
* Control Register
++
*/
++ /* Yukon-Supreme */
++#define FLASH_LDR_CTRL 0x00A4 /* 32
bit Flash Loader */
++ /* Yukon-Supreme */
++#define LD_STATUS_0 0x00A8
/* 32 bit LOADER STATUS */
++ /* Yukon-Supreme */
++#define VPD_FLASH_CTRL 0x00B8 /* 32
bit EEPROM and Flash
++
* Control Register
++
*/
++
++ /* Yukon-FE+ */
++#define OTP_MEM_CTRL_3 0x00BC /* 32
bit LDO Control Register */
++#define PCIE_CAP_ID 0x00C0
/* 8 bit PE Capability ID
++
* Register (PM Cap
++
* ID)
++
*/
++#define PCIE_NPTR 0x00C1
/* 8 bit PE Next Item
++
* Pointer Register
++
*/
++#define PCIE_CAP 0x00C2
/* 16 bit PE Capabilities
++
* Register
++
*/
++#define DEVICE_CAPABILITIES_REGISTER 0x00C4 /* 32 bit Device
Capabilities
++
* Register
++
*/
++#define PCIE_DEVCTRL 0x00C8 /* 16
bit Device Control
++
* Register
++
*/
++#define PCIE_DEVSTAT 0x00CA /* 16
bit Device Status
++
* Register
++
*/
++#define PCIE_LNKCAP 0x00CC
/* 32 bit Link Capabilities
++
* Register
++
*/
++#define PCIE_LNKCTRL 0x00D0 /* 16
bit Link Control
++
* Register
++
*/
++#define PCIE_LNKSTAT 0x00D2 /* 16
bit Link Status Register */
++#define PCIE_DEV_CAP_2 0x00E4 /* 32
bit Device Capabilities
++
* 2 Register
++
*/
++#define PCIE_DEV_CTRL_2 0x00E8 /* 32
bit Device Control 2
++
* Register
++
*/
++#define PCIE_AE_CAP_HDR 0x0100 /* 32
bit Advanced Error
++
* Reporting
++
* Enhanced
++
* Capability Header
++
* Register
++
*/
++#define PCIE_UE_STAT 0x0104 /* 32
bit Uncorrectable Error
++
* Status Register
++
*/
++#define PCIE_UE_MASK 0x0108 /* 32
bit Uncorrectable Error
++
* Mask Register
++
*/
++#define PCIE_UE_SVRT 0x010C /* 32
bit Uncorrectable Error
++
* Severity Register
++
*/
++#define PCIE_CA_STAT 0x0110 /* 32
bit Correctable Error
++
* Status Register
++
*/
++#define PCIE_CA_MASK 0x0114 /* 32
bit Correctable Error
++
* Mask Register
++
*/
++#define PCIE_AE_CAPCTRL 0x0118 /* 32
bit Advanced Error
++
* Capabilities and
++
* Control Register
++
*/
++#define PCIE_HDRLOG_RNG_LO 0x011C /*
Header Log Registers Start */
++#define PCIE_HDRLOG_RNG_HI 0x0128 /*
Header Log Registers End */
++#define PCIE_DEVSERNUMCAP 0x0130 /* 32
bit Device Serial
++
* Number Enhanced
++
* Capability Header
++
*/
++#define PCIE_SERNUM_LOWDW 0x0134 /* 32
bit Serial Number
++
* Register (Lower
++
* DW)
++
*/
++#define PCIE_SERNUM_UPPDW 0x0138 /* 32
bit Serial Number
++
* Register (Upper
++
* DW)
++
*/
++#define PCIE_PWRBDGT_CAPHDR 0x0140 /* 32
bit Power Budgeting
++
* Enhanced
++
* Capability Header
++
*/
++#define PCIE_PWRBDGT_DATASEL 0x0144 /* 32 bit
Power Budgeting
++
* Data Select
++
* Register
++
*/
++#define PCIE_PWRBDGT_DATA 0x0148 /* 32
bit Power Budgeting
++
* Data Register
++
*/
++#define PCIE_PWRBDGT_CAP 0x014C /* 32
bit Power Budgeting
++
* Capability
++
* Register
++
*/
++#define PCIE_TL_CTRL 0x0200 /* 32
bit Transaction Layer
++
* Control Register
++
*/
++#define PCIE_TL_STAT 0x0204 /* 32
bit Transaction Layer
++
* Status Register
++
*/
++#define PCIE_DL_CTRL 0x0208 /* 32
bit Data Link Layer
++
* Control Register
++
*/
++#define PCIE_DL_STAT 0x020C /* 32
bit Data Link Layer
++
* Status Register
++
*/
++#define PCIE_PL_CTRL 0x0210 /* 32
bit PE Physical Layer
++
* Control Register
++
*/
++#define PCIE_PL_STAT 0x0214 /* 32
bit PE Physical Layer
++
* Status Register
++
*/
++#define PCIE_CPLTO 0x0220
/* 32 bit PE Completion
++
* Timeout Register
++
*/
++#define PCIE_FC 0x0224
/* 32 bit PE Flow Control
++
* Register
++
*/
++#define PCIE_ACKTIM_X1 0x0228 /* 32
bit PE Ack Timer for 1x
++
* Link Register
++
*/
++
++/*
++ *
++ * THE BIT DEFINES
++ *
++ */
++/* PCI_VEN_ID 0x0000 Vendor
ID Register */
++#define PCI_VEN_ID_MSK SHIFT0(0xffffU) /* Vendor ID */
++#define PCI_VEN_ID_BASE 0
++
++/* PCI_DEV_ID 0x0002 Device
ID Register */
++#define PCI_DEV_ID_MSK SHIFT0(0xffffU) /* Device ID */
++#define PCI_DEV_ID_BASE 0
++
++/* PCI_CMD 0x0004 Command
Register */
++/* Bit(s) PCI_CMD_RSRV_15_11 reserved */
++#define PCI_CMD_INT_DIS BIT_10S
/* Interrupt Disable */
++/* Bit(s) PCI_CMD_RSRV_9 reserved */
++#define PCI_CMD_SERR_ENA BIT_8S
/* SERR Enable */
++/* Bit(s) PCI_CMD_RSRV_7 reserved */
++#define PCI_CMD_PERREN BIT_6S
/* PERREN */
++/* Bit(s) PCI_CMD_RSRV_5_3 reserved */
++#define PCI_CMD_BMEN BIT_2S
/* BMEN */
++#define PCI_CMD_MEMEN BIT_1S
/* MEMEN */
++#define PCI_CMD_IOEN BIT_0S
/* IOEN */
++
++/* PCI_STAT 0x0006 Status
Register */
++#define PCI_STAT_PERR BIT_15S
/* PERR */
++#define PCI_STAT_SERR BIT_14S
/* SERR */
++#define PCI_STAT_RMABORT BIT_13S
/* RMABORT */
++#define PCI_STAT_RTABORT BIT_12S
/* RTABORT */
++/* Bit(s) PCI_STAT_RSRV_11_9 reserved */
++#define PCI_STAT_DATAPERR BIT_8S
/* DATAPERR */
++/* Bit(s) PCI_STAT_RSRV_7_5 reserved */
++#define PCI_STAT_NEWCAP BIT_4S
/* NEWCAP */
++#define PCI_STAT_INTSTA BIT_3S
/* INTSTA */
++/* Bit(s) PCI_STAT_RSRV_2_0 reserved */
++
++/* PCI_REV_ID 0x0008
Revision ID Register */
++#define PCI_REV_ID_MSK SHIFT0(0xffU) /* Revision ID */
++#define PCI_REV_ID_BASE 0
++
++/* PCI_PIF 0x0009
Programming Interface Register,
++ *
Lower Byte
++ */
++#define PCI_PIF_MSK SHIFT0(0xffU) /* Prog
Interface */
++#define PCI_PIF_BASE 0
++
++/* PCI_SCC 0x000A
Sub-Class Register, Middle Byte */
++#define PCI_SCC_MSK SHIFT0(0xffU) /* Sub Class */
++#define PCI_SCC_BASE 0
++
++/* PCI_BCC 0x000B
Base-Class Register, Upper Byte */
++#define PCI_BCC_MSK SHIFT0(0xffU) /* Base Class */
++#define PCI_BCC_BASE 0
++
++/* PCI_CLS 0x000C Cache
Line Size Register */
++/* Bit(s) PCI_CLS_RSRV_7_0 reserved */
++
++/* PCI_LAT_TIM 0x000D Latency
Timer Register */
++/* Bit(s) PCI_LAT_TIM_RSRV_7_0 reserved */
++
++/* PCI_HDRTYP 0x000E Header
Type Register */
++/* Bit(s) PCI_HDRTYP_RSRV_7_0 reserved */
++
++/* PCI_BIST 0x000F
Built-in Self Test (BIST) Register */
++/* Bit(s) PCI_BIST_RSRV_7_0 reserved */
++
++/* PCI_BAR1_LO 0x0010 Base
Address Register (1st), Lower
++ *
Address
++ */
++#define PCI_BAR1_LO_BASE_MSK SHIFT14(0x3ffff) /*
Lower MEMBASE Address */
++#define PCI_BAR1_LO_BASE_BASE 14
++#define PCI_BAR1_LO_SIZE_MSK SHIFT4(0x3ff) /*
MEMSIZE */
++#define PCI_BAR1_LO_SIZE_BASE 4
++#define PCI_BAR1_LO_PREFEN BIT_3
/* PREFEN */
++#define PCI_BAR1_LO_TYPE_MSK SHIFT1(0x3)
/* Memory Type */
++#define PCI_BAR1_LO_TYPE_BASE 1
++#define PCI_BAR1_LO_IO_SPC BIT_0
/* MEMSPACE */
++
++/* PCI_BAR1_HI 0x0014 Base
Address Register (1st), Upper
++ *
Address
++ */
++#define PCI_BAR1_HI_BASE_MSK SHIFT0(0xffffffff) /*
Upper MEMBASE */
++#define PCI_BAR1_HI_BASE_BASE 0
++
++/* PCI_BAR2 0x0018 Base
Address Register (2nd) */
++#define PCI_BAR2_BASE_MSK SHIFT8(0xffffff) /*
IOBASE */
++#define PCI_BAR2_BASE_BASE 8
++#define PCI_BAR2_SIZE_MSK SHIFT2(0x3f) /*
IOSIZE */
++#define PCI_BAR2_SIZE_BASE 2
++/* Bit(s) PCI_BAR2_RSRV_1 reserved */
++#define PCI_BAR2_IO_SPC BIT_0
/* IOSPACE */
++
++/* PCI_SSVEN_ID 0x002C Subsystem
Vendor ID Register */
++#define PCI_SSVEN_ID_MSK SHIFT0(0xffffU) /* Subsystem
Vendor ID */
++#define PCI_SSVEN_ID_BASE 0
++
++/* PCI_SSDEV_ID 0x002E Subsystem ID
Register */
++#define PCI_SSDEV_ID_MSK SHIFT0(0xffffU) /* Subsystem ID
*/
++#define PCI_SSDEV_ID_BASE 0
++
++/* PCI_ERBAR 0x0030
Expansion Rom Base Address Register */
++#define PCI_ERBAR_BASE_MSK SHIFT17(0x7fff)
/* Rombase */
++#define PCI_ERBAR_BASE_BASE 17
++#define PCI_ERBAR_BASE_SIZE_MSK SHIFT14(0x7) /*
Rombase/size */
++#define PCI_ERBAR_BASE_SIZE_BASE 14
++#define PCI_ERBAR_SIZE_MSK SHIFT11(0x7)
/* Romsize */
++#define PCI_ERBAR_SIZE_BASE 11
++/* Bit(s) PCI_ERBAR_RSRV_10_1 reserved */
++#define PCI_ERBAR_ENA BIT_0
/* ROMEN */
++
++/* PCI_NCAP_PTR 0x0034 New
Capabilities Pointer (New Cap
++ *
Ptr) Register
++ */
++#define PCI_NCAP_PTR_MSK SHIFT0(0xffU) /* New
Capabilities Pointer */
++#define PCI_NCAP_PTR_BASE 0
++
++/* PCI_INT_LINE 0x003C Interrupt Line
Register */
++#define PCI_INT_LINE_MSK SHIFT0(0xffU) /* Interrupt
Line */
++#define PCI_INT_LINE_BASE 0
++
++/* PCI_INT_PIN 0x003D
Interrupt Pin Register */
++#define PCI_INT_PIN_MSK SHIFT0(0xffU) /* Interrupt
Pin */
++#define PCI_INT_PIN_BASE 0
++
++/* PCI_MIN_GNT 0x003E Min_Gnt
Register */
++/* Bit(s) PCI_MIN_GNT_RSRV_7_0 reserved */
++
++/* PCI_MAX_LAT 0x003F Max_Lat
Register */
++/* Bit(s) PCI_MAX_LAT_RSRV_7_0 reserved */
++
++/* PCI_OUR1 0x0040 Our
Register 1 */
++/* Bit(s) PCI_OUR1_RSRV_31 reserved */
++#define PCI_OUR1_SW_POR BIT_30
/* SW POR */
++/* Enable Gen Preset during SW POR */
++#define PCI_OUR1_EN_GEN_PRSET BIT_29
++#define PCI_OUR1_GP_COMA BIT_28
/* PHY Coma Mode */
++#define PCI_OUR1_DIS_SPI_LOAD BIT_27
/* Disable SPI Loader */
++#define PCI_OUR1_GP_PWD BIT_26
/* PHY Power Down Mode */
++#define PCI_OUR1_DIS_VPD_LOAD BIT_25
/* Disable VPD Loader */
++#define PCI_OUR1_ENBOOT BIT_24
/* En Boot */
++#define PCI_OUR1_ENIOMAP BIT_23
/* En IO Mapping */
++#define PCI_OUR1_ENEPROM BIT_22
/* En Eprom */
++#define PCI_OUR1_PAGE_SIZ_MSK SHIFT20(0x3) /*
Pagesize<1:0> */
++#define PCI_OUR1_PAGE_SIZ_BASE 20
++ /* Yukon-Supreme */
++#define PCI_OUR1_ROM_SRC_SEL BIT_19
/* ROM Source Select */
++#define PCI_OUR1_PAGE_SEL_MSK SHIFT16(0x7) /* Page
Reg<2:0> */
++#define PCI_OUR1_PAGE_SEL_BASE 16
++#define PCI_OUR1_DBG_PEX_PME BIT_15
/* DEBUG_PEX_PME */
++/* Bit(s) PCI_OUR1_RSRV_14_10 reserved */
++/* Timer for GPHY Link Trigger */
++#define PCI_OUR1_GP_TRIG_TIM_MSK SHIFT8(0x3)
++#define PCI_OUR1_GP_TRIG_TIM_BASE 8
++#define PCI_OUR1_L1_EVT_ENA BIT_7
/* L1 Event Enable */
++#define PCI_OUR1_GP_LNK_ENA BIT_6
/* Enable GPHY Link */
++#define PCI_OUR1_FORCE_L1 BIT_5
/* Force to L1 */
++/* Bit(s) PCI_OUR1_RSRV_4_1 reserved */
++/* PCIE Receiver Overflow Control */
++#define PCI_OUR1_PEX_RX_OF_CTRL BIT_0
++
++/* PCI_OUR2 0x0044 Our
Register 2 */
++/* Bit(s) PCI_OUR2_RSRV_31_24 reserved */
++#define PCI_OUR2_VPD_DEVSEL_MSK SHIFT17(0x7f) /* VPD
Devsel */
++#define PCI_OUR2_VPD_DEVSEL_BASE 17
++#define PCI_OUR2_VPD_ROMSIZE_MSK SHIFT14(0x7) /* VPD
ROM Size */
++#define PCI_OUR2_VPD_ROMSIZE_BASE 14
++/* Bit(s) PCI_OUR2_RSRV_13_0 reserved */
++
++/* PCI_PM_CAP_ID 0x0048 Power
Management Capability ID
++ *
Register (PM Cap ID)
++ */
++#define PCI_PM_CAP_ID_MSK SHIFT0(0xffU) /* Cap ID */
++#define PCI_PM_CAP_ID_BASE 0
++
++/* PCI_PM_NXT_PTR 0x0049 Power
Management Next Item Pointer
++ *
Register
++ */
++#define PCI_PM_NXT_PTR_MSK SHIFT0(0xffU) /* Next Item
Ptr */
++#define PCI_PM_NXT_PTR_BASE 0
++
++/* PCI_PM_CAP 0x004A Power
Management Capabilities
++ *
Register
++ */
++#define PCI_PM_CAP_D3C_ENA BIT_15S
/* PME Support */
++#define PCI_PM_CAP_D3H_ENA BIT_14S
/* PME Support */
++#define PCI_PM_CAP_D2_ENA BIT_13S
/* PME Support */
++#define PCI_PM_CAP_D1_ENA BIT_12S
/* PME Support */
++#define PCI_PM_CAP_D0_ENA BIT_11S
/* PME Support */
++#define PCI_PM_CAP_D2_SUP BIT_10S
/* D2 Support */
++#define PCI_PM_CAP_D1_SUP BIT_9S
/* D1 Support */
++/* Bit(s) PCI_PM_CAP_RSRV_8_6 reserved */
++#define PCI_PM_CAP_DSI_ENA BIT_5S
/* DSI */
++/* Bit(s) PCI_PM_CAP_RSRV_4_3 reserved */
++#define PCI_PM_CAP_VER_ID_MSK SHIFT0(0x7U) /*
Version */
++#define PCI_PM_CAP_VER_ID_BASE 0
++
++/* PCI_PM_CSR 0x004C Power
Management Control/Status
++ *
Register
++ */
++#define PCI_PM_CSR_PME_STAT BIT_15S
/* PME Status */
++#define PCI_PM_CSR_D_SCALE_MSK SHIFT13(0x3U) /* Data
Scale */
++#define PCI_PM_CSR_D_SCALE_BASE 13
++#define PCI_PM_CSR_D_SEL_MSK SHIFT9(0xfU) /* Data
Select */
++#define PCI_PM_CSR_D_SEL_BASE 9
++#define PCI_PM_CSR_PMEEN BIT_8S
/* PME En */
++/* Bit(s) PCI_PM_CSR_RSRV_7_2 reserved */
++#define PCI_PM_CSR_PWST_MSK SHIFT0(0x3U)
/* Power State */
++#define PCI_PM_CSR_PWST_BASE 0
++
++/* PCI_PM_DATA 0x004F Power
Management Data Register */
++#define PCI_PM_DATA_MSK SHIFT0(0xffU) /* Data */
++#define PCI_PM_DATA_BASE 0
++
++/* PCI_VPD_CAP_ID 0x0050 VPD Capability
ID Register (VPD
++ *
Cap ID)
++ */
++#define PCI_VPD_CAP_ID_MSK SHIFT0(0xffU) /* Cap ID */
++#define PCI_VPD_CAP_ID_BASE 0
++
++/* PCI_VPD_NPTR 0x0051 VPD Next Item
Pointer Register */
++#define PCI_VPD_NPTR_MSK SHIFT0(0xffU) /* Next Item
Ptr */
++#define PCI_VPD_NPTR_BASE 0
++
++/* PCI_VPD_ADDR 0x0052 VPD Address
Register */
++#define PCI_VPD_ADDR_FLAG BIT_15S /* Flag
*/
++#define PCI_VPD_ADDR_MSK SHIFT0(0x7fffU) /* VPD Address
*/
++#define PCI_VPD_ADDR_BASE 0
++
++/* PCI_VPD_DATA 0x0054 VPD Data
Register */
++#define PCI_VPD_DATA_MSK SHIFT0(0xffffffff) /* VPD
Data */
++#define PCI_VPD_DATA_BASE 0
++
++/* PCI_LDR_CTRL 0x0058 TWSI EEPROM
Loader Control Register */
<<Diff was trimmed, longer than 597 lines>>
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