Author: marcus Date: Mon Nov 3 08:46:19 2008 GMT
Module: SOURCES Tag: HEAD
---- Log message:
- up to 1.23
---- Files affected:
SOURCES:
linux-nvidia.patch (1.1 -> 1.2)
---- Diffs:
================================================================
Index: SOURCES/linux-nvidia.patch
diff -u SOURCES/linux-nvidia.patch:1.1 SOURCES/linux-nvidia.patch:1.2
--- SOURCES/linux-nvidia.patch:1.1 Sat Jun 23 20:28:34 2007
+++ SOURCES/linux-nvidia.patch Mon Nov 3 09:46:13 2008
@@ -1,7 +1,7 @@
diff -uNr linux-2.6.16.orig/drivers/net/forcedeth.c
linux-2.6.16/drivers/net/forcedeth.c
---- linux-2.6.16.orig/drivers/net/forcedeth.c 2007-06-23 20:16:01.572248000
+0200
-+++ linux-2.6.16/drivers/net/forcedeth.c 2006-10-21 14:44:00.000000000
+0200
-@@ -102,6 +102,17 @@
+--- linux-2.6.16.orig/drivers/net/forcedeth.c 2006-03-20 06:53:29.000000000
+0100
++++ linux-2.6.16/drivers/net/forcedeth.c 2008-11-02 20:40:40.000000000
+0100
+@@ -102,6 +102,19 @@
* 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
* 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
* 0.49: 10 Dec 2005: Fix tso for large buffers.
@@ -16,23 +16,28 @@
+ * 0.58: 20 May 2006: Optimized rx and tx data paths.
+ * 0.59: 31 May 2006: Added support for sideband management unit.
+ * 0.60: 31 May 2006: Added support for recoverable error.
++ * 0.61: 18 Jul 2006: Added support for suspend/resume.
++ * 0.62: 16 Jan 2007: Fixed statistics, mgmt communication, and low phy
speed on S5.
*
* Known bugs:
* We suspect that on some hardware no TX done interrupts are generated.
-@@ -113,7 +124,7 @@
+@@ -113,8 +126,9 @@
* DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
* superfluous timer interrupts from the nic.
*/
-#define FORCEDETH_VERSION "0.49"
-+#define FORCEDETH_VERSION "0.60-Driver Package V1.21"
++#define FORCEDETH_VERSION "0.62-Driver Package V1.23"
#define DRV_NAME "forcedeth"
++#define DRV_DATE "2007/04/06"
#include <linux/module.h>
-@@ -131,34 +142,189 @@
+ #include <linux/types.h>
+@@ -131,18 +145,240 @@
#include <linux/random.h>
#include <linux/init.h>
#include <linux/if_vlan.h>
+#include <linux/rtnetlink.h>
++#include <linux/reboot.h>
+#include <linux/version.h>
+
+#define RHES3 0
@@ -40,9 +45,11 @@
+#define RHES4 2
+#define SUSE10 3
+#define FEDORA5 4
++#define FEDORA6 5
+
-+
-+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13)
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17)
++#define NVVER FEDORA6
++#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13)
+#define NVVER FEDORA5
+#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
+#define NVVER SUSE10
@@ -72,6 +79,8 @@
#define dprintk(x...) do { } while (0)
#endif
++#define DPRINTK(nlevel,klevel,args...) (void)((debug & NETIF_MSG_##nlevel) &&
printk(klevel args))
++
+/* it should add in pci_ids.h */
+#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_12
+#define PCI_DEVICE_ID_NVIDIA_NVENET_12 0x0268
@@ -109,6 +118,42 @@
+#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_23
+#define PCI_DEVICE_ID_NVIDIA_NVENET_23 0x0453
+#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_24
++#define PCI_DEVICE_ID_NVIDIA_NVENET_24 0x054c
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_25
++#define PCI_DEVICE_ID_NVIDIA_NVENET_25 0x054d
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_26
++#define PCI_DEVICE_ID_NVIDIA_NVENET_26 0x054e
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_27
++#define PCI_DEVICE_ID_NVIDIA_NVENET_27 0x054f
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_28
++#define PCI_DEVICE_ID_NVIDIA_NVENET_28 0x07DC
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_29
++#define PCI_DEVICE_ID_NVIDIA_NVENET_29 0x07DD
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_30
++#define PCI_DEVICE_ID_NVIDIA_NVENET_30 0x07DE
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_31
++#define PCI_DEVICE_ID_NVIDIA_NVENET_31 0x07DF
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_32
++#define PCI_DEVICE_ID_NVIDIA_NVENET_32 0x0760
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_33
++#define PCI_DEVICE_ID_NVIDIA_NVENET_33 0x0761
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_34
++#define PCI_DEVICE_ID_NVIDIA_NVENET_34 0x0762
++#endif
++#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_35
++#define PCI_DEVICE_ID_NVIDIA_NVENET_35 0x0763
++#endif
+
+/* it should add in mii.h */
+#ifndef ADVERTISE_1000HALF
@@ -161,6 +206,26 @@
+#define __iomem
+#endif
+
++#ifndef __bitwise
++#define __bitwise
++#endif
++
++#ifndef __force
++#define __force
++#endif
++
++#ifndef PCI_D0
++#define PCI_D0 ((int __bitwise __force) 0)
++#endif
++
++#ifndef PM_EVENT_SUSPEND
++#define PM_EVENT_SUSPEND 2
++#endif
++
++#if NVVER < SUSE10
++#define pm_message_t u32
++#endif
++
+/* rx/tx mac addr + type + vlan + align + slack*/
+#ifndef RX_NIC_BUFSIZE
+#define RX_NIC_BUFSIZE (ETH_DATA_LEN + 64)
@@ -182,15 +247,34 @@
+ u16 entry; /* driver uses to specify entry, OS writes */
+};
+#endif
++
++#ifndef PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET
++#define PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET 0x00
++#endif
++
++#ifndef PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET
++#define PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET 0x04
++#endif
++
++#ifndef PCI_MSIX_ENTRY_DATA_OFFSET
++#define PCI_MSIX_ENTRY_DATA_OFFSET 0x08
++#endif
++
++#ifndef PCI_MSIX_ENTRY_SIZE
++#define PCI_MSIX_ENTRY_SIZE 16
++#endif
++
++#ifndef PCI_MSIX_FLAGS_BIRMASK
++#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
++#endif
++
++#ifndef PCI_CAP_ID_MSIX
++#define PCI_CAP_ID_MSIX 0x11
++#endif
/*
* Hardware access:
- */
-
--#define DEV_NEED_TIMERIRQ 0x0000 /* work-around for Wake-On-Lan */
--#define DEV_NEED_TIMERIRQ_ORIG 0x0001 /* set the timer irq flag in
the irq mask */
-+#define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq
mask */
- #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the
timer irq */
+@@ -153,11 +389,40 @@
#define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and
needs packet format 2 */
#define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
#define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum
offloads */
@@ -199,9 +283,11 @@
+#define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */
+#define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */
+#define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */
-+#define DEV_HAS_STATISTICS 0x0400 /* device supports hw statistics */
-+#define DEV_HAS_TEST_EXTENDED 0x0800 /* device supports extended
diagnostic test */
-+#define DEV_HAS_MGMT_UNIT 0x1000 /* device supports management unit */
++#define DEV_HAS_STATISTICS_V1 0x0400 /* device supports hw statistics
version 1 */
++#define DEV_HAS_STATISTICS_V2 0x0800 /* device supports hw statistics
version 2 */
++#define DEV_HAS_TEST_EXTENDED 0x1000 /* device supports extended
diagnostic test */
++#define DEV_HAS_MGMT_UNIT 0x2000 /* device supports management unit */
++#define DEV_HAS_CORRECT_MACADDR 0x4000 /* device supports correct mac
address */
+
+#define NVIDIA_ETHERNET_ID(deviceid,nv_driver_data) {\
+ .vendor = PCI_VENDOR_ID_NVIDIA, \
@@ -213,6 +299,14 @@
+
+#define Mv_LED_Control 16
+#define Mv_Page_Address 22
++#define Mv_LED_FORCE_OFF 0x88
++#define Mv_LED_DUAL_MODE3 0x40
++
++struct nvmsi_msg{
++ u32 address_lo;
++ u32 address_hi;
++ u32 data;
++};
enum {
NvRegIrqStatus = 0x000,
@@ -222,7 +316,7 @@
NvRegIrqMask = 0x004,
#define NVREG_IRQ_RX_ERROR 0x0001
#define NVREG_IRQ_RX 0x0002
-@@ -167,14 +333,18 @@
+@@ -166,14 +431,18 @@
#define NVREG_IRQ_TX_OK 0x0010
#define NVREG_IRQ_TIMER 0x0020
#define NVREG_IRQ_LINK 0x0040
@@ -245,7 +339,7 @@
NvRegUnknownSetupReg6 = 0x008,
#define NVREG_UNKSETUP6_VAL 3
-@@ -186,25 +356,45 @@
+@@ -185,25 +454,45 @@
NvRegPollingInterval = 0x00c,
#define NVREG_POLL_DEFAULT_THROUGHPUT 970
#define NVREG_POLL_DEFAULT_CPU 13
@@ -292,7 +386,7 @@
NvRegReceiverStatus = 0x98,
#define NVREG_RCVSTAT_BUSY 0x01
-@@ -214,10 +404,12 @@
+@@ -213,10 +502,12 @@
#define NVREG_RNDSEED_FORCE2 0x2d00
#define NVREG_RNDSEED_FORCE3 0x7400
@@ -309,7 +403,7 @@
NvRegMacAddrA = 0xA8,
NvRegMacAddrB = 0xAC,
NvRegMulticastAddrA = 0xB0,
-@@ -234,7 +426,8 @@
+@@ -233,7 +524,8 @@
NvRegRingSizes = 0x108,
#define NVREG_RINGSZ_TXSHIFT 0
#define NVREG_RINGSZ_RXSHIFT 16
@@ -319,7 +413,7 @@
NvRegLinkSpeed = 0x110,
#define NVREG_LINKSPEED_FORCE 0x10000
#define NVREG_LINKSPEED_10 1000
-@@ -243,8 +436,10 @@
+@@ -242,8 +534,10 @@
#define NVREG_LINKSPEED_MASK (0xFFF)
NvRegUnknownSetupReg5 = 0x130,
#define NVREG_UNKSETUP5_BIT31 (1<<31)
@@ -332,7 +426,7 @@
NvRegTxRxControl = 0x144,
#define NVREG_TXRXCTL_KICK 0x0001
#define NVREG_TXRXCTL_BIT1 0x0002
-@@ -253,15 +448,22 @@
+@@ -252,15 +546,22 @@
#define NVREG_TXRXCTL_RESET 0x0010
#define NVREG_TXRXCTL_RXCHECK 0x0400
#define NVREG_TXRXCTL_DESC_1 0
@@ -359,7 +453,7 @@
NvRegAdapterControl = 0x188,
#define NVREG_ADAPTCTL_START 0x02
-@@ -291,6 +493,7 @@
+@@ -290,6 +591,7 @@
#define NVREG_WAKEUPFLAGS_ENABLE 0x1111
NvRegPatternCRC = 0x204,
@@ -367,7 +461,7 @@
NvRegPatternMask = 0x208,
NvRegPowerCap = 0x268,
#define NVREG_POWERCAP_D3SUPP (1<<30)
-@@ -304,6 +507,43 @@
+@@ -303,6 +605,43 @@
#define NVREG_POWERSTATE_D1 0x0001
#define NVREG_POWERSTATE_D2 0x0002
#define NVREG_POWERSTATE_D3 0x0003
@@ -411,7 +505,7 @@
};
/* Big endian: should work, but is untested */
-@@ -315,7 +555,7 @@
+@@ -314,7 +653,7 @@
struct ring_desc_ex {
u32 PacketBufferHigh;
u32 PacketBufferLow;
@@ -420,7 +514,7 @@
u32 FlagLen;
};
-@@ -336,7 +576,7 @@
+@@ -335,7 +674,7 @@
#define NV_TX_CARRIERLOST (1<<27)
#define NV_TX_LATECOLLISION (1<<28)
#define NV_TX_UNDERFLOW (1<<29)
@@ -429,7 +523,7 @@
#define NV_TX_VALID (1<<31)
#define NV_TX2_LASTPACKET (1<<29)
-@@ -347,7 +587,7 @@
+@@ -346,7 +685,7 @@
#define NV_TX2_LATECOLLISION (1<<27)
#define NV_TX2_UNDERFLOW (1<<28)
/* error and valid are the same for both */
@@ -438,7 +532,7 @@
#define NV_TX2_VALID (1<<31)
#define NV_TX2_TSO (1<<28)
#define NV_TX2_TSO_SHIFT 14
-@@ -356,6 +596,8 @@
+@@ -355,6 +694,8 @@
#define NV_TX2_CHECKSUM_L3 (1<<27)
#define NV_TX2_CHECKSUM_L4 (1<<26)
@@ -447,7 +541,7 @@
#define NV_RX_DESCRIPTORVALID (1<<16)
#define NV_RX_MISSEDFRAME (1<<17)
#define NV_RX_SUBSTRACT1 (1<<18)
-@@ -366,7 +608,7 @@
+@@ -365,7 +706,7 @@
#define NV_RX_CRCERR (1<<27)
#define NV_RX_OVERFLOW (1<<28)
#define NV_RX_FRAMINGERR (1<<29)
@@ -456,7 +550,7 @@
#define NV_RX_AVAIL (1<<31)
#define NV_RX2_CHECKSUMMASK (0x1C000000)
-@@ -383,11 +625,15 @@
+@@ -382,11 +723,16 @@
#define NV_RX2_OVERFLOW (1<<23)
#define NV_RX2_FRAMINGERR (1<<24)
/* error and avail are the same for both */
@@ -470,11 +564,12 @@
/* Miscelaneous hardware related defines: */
-#define NV_PCI_REGSZ 0x270
+#define NV_PCI_REGSZ_VER1 0x270
-+#define NV_PCI_REGSZ_VER2 0x604
++#define NV_PCI_REGSZ_VER2 0x2d4
++#define NV_PCI_REGSZ_VER3 0x604
/* various timeout delays: all in usec */
#define NV_TXRX_RESET_DELAY 4
-@@ -404,6 +650,7 @@
+@@ -403,6 +749,7 @@
#define NV_MIIBUSY_DELAY 50
#define NV_MIIPHY_DELAY 10
#define NV_MIIPHY_DELAYMAX 10000
@@ -482,7 +577,7 @@
#define NV_WAKEUPPATTERNS 5
#define NV_WAKEUPMASKENTRIES 4
-@@ -411,16 +658,18 @@
+@@ -410,16 +757,18 @@
/* General driver defaults */
#define NV_WATCHDOG_TIMEO (5*HZ)
@@ -509,7 +604,7 @@
/* rx/tx mac addr + type + vlan + align + slack*/
#define NV_RX_HEADERS (64)
-@@ -434,6 +683,7 @@
+@@ -433,6 +782,7 @@
#define OOM_REFILL (1+HZ/20)
#define POLL_WAIT (1+HZ/100)
#define LINK_TIMEOUT (3*HZ)
@@ -517,7 +612,7 @@
/*
* desc_ver values:
-@@ -449,16 +699,37 @@
+@@ -448,16 +798,38 @@
/* PHY defines */
#define PHY_OUI_MARVELL 0x5043
#define PHY_OUI_CICADA 0x03f1
@@ -534,6 +629,7 @@
-#define PHY_INIT6 0x02000
+#define PHYID2_MODEL_MASK 0x03f0
+#define PHY_MODEL_MARVELL_E3016 0x220
++#define PHY_MODEL_MARVELL_E1011 0xb0
+#define PHY_MARVELL_E3016_INITMASK 0x0300
+#define PHY_CICADA_INIT1 0x0f000
+#define PHY_CICADA_INIT2 0x0e00
@@ -561,7 +657,7 @@
#define PHY_GIGABIT 0x0100
#define PHY_TIMEOUT 0x1
-@@ -468,14 +739,148 @@
+@@ -467,14 +839,148 @@
#define PHY_1000 0x2
#define PHY_HALF 0x100
@@ -593,9 +689,6 @@
+#define NV_MSI_X_VECTOR_TX 0x1
+#define NV_MSI_X_VECTOR_OTHER 0x2
+
-+/* statistics */
-+#define NV_STATS_COUNT_SW 10
-+
+#define NVLAN_DISABLE_ALL_FEATURES do { \
+ msi = NV_MSI_INT_DISABLED; \
+ msix = NV_MSIX_INT_DISABLED; \
@@ -682,6 +775,9 @@
+ u64 rx_pause;
+ u64 rx_drop_frame;
+};
++#define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct
nv_ethtool_stats)/sizeof(u64))
++#define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 4)
++#define NV_DEV_STATISTICS_SW_COUNT 10
+
+/* diagnostics */
+#define NV_TEST_COUNT_BASE 3
@@ -693,7 +789,7 @@
+ { "interrupt (offline) " },
+ { "loopback (offline) " }
+};
-+
+
+struct register_test {
+ u32 reg;
+ u32 mask;
@@ -708,7 +804,7 @@
+ { NvRegWakeUpFlags, 0x07777 },
+ { 0,0 }
+};
-
++
+struct nv_skb_map {
+ struct sk_buff *skb;
+ dma_addr_t dma;
@@ -717,7 +813,7 @@
/*
* SMP locking:
-@@ -490,11 +895,48 @@
+@@ -489,57 +995,105 @@
/* in dev: base, irq */
struct fe_priv {
@@ -766,7 +862,9 @@
int in_shutdown;
u32 linkspeed;
int duplex;
-@@ -503,44 +945,46 @@
++ int speed_duplex;
+ int autoneg;
+ int fixed_mode;
int phyaddr;
int wolenabled;
unsigned int phy_oui;
@@ -829,10 +927,18 @@
+ /* flow control */
+ u32 pause_flags;
+ u32 led_stats[3];
++ u32 saved_config_space[64];
++ u32 saved_nvregphyinterface;
++#if NVVER < SUSE10
++ u32 pci_state[16];
++#endif
++ /* msix table */
++ struct nvmsi_msg nvmsg[NV_MSI_X_MAX_VECTORS];
++ unsigned long msix_pa_addr;
};
/*
-@@ -555,8 +999,10 @@
+@@ -554,8 +1108,10 @@
* Throughput Mode: Every tx and rx packet will generate an interrupt.
* CPU Mode: Interrupts are controlled by a timer.
*/
@@ -845,7 +951,7 @@
static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
/*
-@@ -568,14 +1014,213 @@
+@@ -567,14 +1123,221 @@
*/
static int poll_interval = -1;
@@ -990,6 +1096,14 @@
+};
+static int tagging_8021pq = NV_8021PQ_ENABLED;
+
++enum {
++ NV_LOW_POWER_DISABLED,
++ NV_LOW_POWER_ENABLED
++};
++static int lowpowerspeed = NV_LOW_POWER_ENABLED;
++
++static int debug = 0;
++
+#if NVVER < RHES4
+static inline unsigned long nv_msecs_to_jiffies(const unsigned int m)
+{
@@ -1060,7 +1174,7 @@
}
static inline void pci_push(u8 __iomem *base)
-@@ -613,78 +1258,247 @@
+@@ -612,22 +1375,137 @@
return 0;
}
@@ -1085,7 +1199,6 @@
- reg = readl(base + NvRegMIIControl);
- if (reg & NVREG_MIICTL_INUSE) {
- writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
-- udelay(NV_MIIBUSY_DELAY);
+ if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
+ if (rxtx_flags & NV_SETUP_RX_RING) {
+ writel((u32) cpu_to_le64(np->ring_addr), base +
NvRegRxRingPhysAddr);
@@ -1102,59 +1215,30 @@
+ writel((u32) cpu_to_le64(np->ring_addr +
np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
+ writel((u32) (cpu_to_le64(np->ring_addr +
np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base +
NvRegTxRingPhysAddrHigh);
+ }
- }
++ }
+}
-
-- reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
-- if (value != MII_READ) {
-- writel(value, base + NvRegMIIData);
-- reg |= NVREG_MIICTL_WRITE;
-- }
-- writel(reg, base + NvRegMIIControl);
++
+static void free_rings(struct net_device *dev)
+{
+ struct fe_priv *np = get_nvpriv(dev);
-
-- if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
-- NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
-- dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed
out.\n",
-- dev->name, miireg, addr);
-- retval = -1;
-- } else if (value != MII_READ) {
-- /* it was a write operation - fewer failures are detectable */
-- dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY
%d\n",
-- dev->name, value, miireg, addr);
-- retval = 0;
-- } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
-- dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
-- dev->name, miireg, addr);
-- retval = -1;
++
+ if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
+ if(np->rx_ring.orig)
+ pci_free_consistent(np->pci_dev, sizeof(struct
ring_desc) * (np->rx_ring_size + np->tx_ring_size),
+ np->rx_ring.orig, np->ring_addr);
- } else {
-- retval = readl(base + NvRegMIIData);
-- dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d:
0x%x.\n",
-- dev->name, miireg, addr, retval);
++ } else {
+ if (np->rx_ring.ex)
+ pci_free_consistent(np->pci_dev, sizeof(struct
ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
+ np->rx_ring.ex, np->ring_addr);
- }
--
-- return retval;
++ }
+ if (np->rx_skb)
+ kfree(np->rx_skb);
+ if (np->tx_skb)
+ kfree(np->tx_skb);
- }
-
--static int phy_reset(struct net_device *dev)
++}
++
+static int using_multi_irqs(struct net_device *dev)
- {
-- struct fe_priv *np = netdev_priv(dev);
-- u32 miicontrol;
-- unsigned int tries = 0;
++{
+ struct fe_priv *np = get_nvpriv(dev);
+
+ if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
@@ -1169,7 +1253,7 @@
+{
+ struct fe_priv *np = get_nvpriv(dev);
+
-+ dprintk(KERN_DEBUG "%s: nv_enable_irq: begin\n",dev->name);
++ dprintk(KERN_DEBUG "%s:%s\n",dev->name,__FUNCTION__);
+ /* modify network device class id */
+ if (!using_multi_irqs(dev)) {
+ if (np->msi_flags & NV_MSI_X_ENABLED)
@@ -1187,7 +1271,7 @@
+{
+ struct fe_priv *np = get_nvpriv(dev);
+
<<Diff was trimmed, longer than 597 lines>>
---- CVS-web:
http://cvs.pld-linux.org/cgi-bin/cvsweb.cgi/SOURCES/linux-nvidia.patch?r1=1.1&r2=1.2&f=u
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