Author: blekot Date: Thu Mar 2 19:10:00 2006 GMT
Module: SOURCES Tag: AC-branch
---- Log message:
- new
- fixes http://gcc.gnu.org/bugzilla/show_bug.cgi?id=10984
- broke build (needs revert)
---- Files affected:
SOURCES:
gcc-x86-sse2-bug.patch (NONE -> 1.1.2.1) (NEW)
---- Diffs:
================================================================
Index: SOURCES/gcc-x86-sse2-bug.patch
diff -u /dev/null SOURCES/gcc-x86-sse2-bug.patch:1.1.2.1
--- /dev/null Thu Mar 2 20:10:00 2006
+++ SOURCES/gcc-x86-sse2-bug.patch Thu Mar 2 20:09:55 2006
@@ -0,0 +1,138 @@
+===================================================================
+retrieving revision 1.350
+retrieving revision 1.351
+diff -u -r1.350 -r1.351
+--- gcc/gcc/config/i386/i386.h 2003/07/11 14:09:29 1.350
++++ gcc/gcc/config/i386/i386.h 2003/08/23 21:18:57 1.351
+@@ -3018,6 +3018,10 @@
+ {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
+ {"const1_operand", {CONST_INT}}, \
+ {"const248_operand", {CONST_INT}}, \
++ {"const_0_to_3_operand", {CONST_INT}}, \
++ {"const_0_to_7_operand", {CONST_INT}}, \
++ {"const_0_to_15_operand", {CONST_INT}}, \
++ {"const_0_to_255_operand", {CONST_INT}}, \
+ {"incdec_operand", {CONST_INT}}, \
+ {"mmx_reg_operand", {REG}}, \
+ {"reg_no_sp_operand", {SUBREG, REG}},
\
+===================================================================
+RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.md,v
+retrieving revision 1.480
+retrieving revision 1.481
+diff -u -r1.480 -r1.481
+--- gcc/gcc/config/i386/i386.md 2003/07/28 18:13:57 1.480
++++ gcc/gcc/config/i386/i386.md 2003/08/23 21:18:58 1.481
+@@ -3278,22 +3278,56 @@
+ ")
+
+ (define_insn "zero_extendsidi2_32"
+- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
+- (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r")))
++ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
++ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
"0,rm,r,m,m")))
+ (clobber (reg:CC 17))]
+- "!TARGET_64BIT"
+- "#"
+- [(set_attr "mode" "SI")])
++ "!TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
++ "@
++ #
++ #
++ #
++ movd\t{%1, %0|%0, %1}
++ movd\t{%1, %0|%0, %1}"
++ [(set_attr "mode" "SI,SI,SI,DI,TI")
++ (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
++
++(define_insn "*zero_extendsidi2_32_1"
++ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
++ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
"0,rm,r,rm,rm")))
++ (clobber (reg:CC 17))]
++ "!TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
++ "@
++ #
++ #
++ #
++ movd\t{%1, %0|%0, %1}
++ movd\t{%1, %0|%0, %1}"
++ [(set_attr "mode" "SI,SI,SI,DI,TI")
++ (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
+
+ (define_insn "zero_extendsidi2_rex64"
+- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
+- (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))]
+- "TARGET_64BIT"
++ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!?Y")
++ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,m,m")))]
++ "TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
+ "@
+ mov\t{%k1, %k0|%k0, %k1}
+- #"
+- [(set_attr "type" "imovx,imov")
+- (set_attr "mode" "SI,DI")])
++ #
++ movd\t{%1, %0|%0, %1}
++ movd\t{%1, %0|%0, %1}"
++ [(set_attr "type" "imovx,imov,mmxmov,ssemov")
++ (set_attr "mode" "SI,DI,DI,TI")])
++
++(define_insn "*zero_extendsidi2_rex64_1"
++ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!*?")
++ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
"rm,0,rm,rm")))]
++ "TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
++ "@
++ mov\t{%k1, %k0|%k0, %k1}
++ #
++ movd\t{%1, %0|%0, %1}
++ movd\t{%1, %0|%0, %1}"
++ [(set_attr "type" "imovx,imov,mmxmov,ssemov")
++ (set_attr "mode" "SI,DI,SI,SI")])
+
+ (define_split
+ [(set (match_operand:DI 0 "memory_operand" "")
+@@ -3315,7 +3349,8 @@
+ [(set (match_operand:DI 0 "nonimmediate_operand" "")
+ (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
+ (clobber (reg:CC 17))]
+- "!TARGET_64BIT && reload_completed"
++ "!TARGET_64BIT && reload_completed
++ && !SSE_REG_P (operands[0]) && !MMX_REG_P (operands[0])"
+ [(set (match_dup 3) (match_dup 1))
+ (set (match_dup 4) (const_int 0))]
+ "split_di (&operands[0], 1, &operands[3], &operands[4]);")
+@@ -21228,7 +21263,7 @@
+ (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
+ (vec_duplicate:V4HI
+ (truncate:HI (match_operand:SI 2
"nonimmediate_operand" "rm")))
+- (match_operand:SI 3 "immediate_operand" "i")))]
++ (match_operand:SI 3 "const_0_to_15_operand" "N")))]
+ "TARGET_SSE || TARGET_3DNOW_A"
+ "pinsrw\t{%3, %2, %0|%0, %2, %3}"
+ [(set_attr "type" "mmxcvt")
+@@ -21238,7 +21273,7 @@
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (zero_extend:SI (vec_select:HI (match_operand:V4HI 1
"register_operand" "y")
+ (parallel
+- [(match_operand:SI 2
"immediate_operand" "i")]))))]
++ [(match_operand:SI 2
"const_0_to_3_operand" "N")]))))]
+ "TARGET_SSE || TARGET_3DNOW_A"
+ "pextrw\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "type" "mmxcvt")
+@@ -22924,7 +22959,7 @@
+ (vec_duplicate:V8HI
+ (truncate:HI
+ (match_operand:SI 2 "nonimmediate_operand" "rm")))
+- (match_operand:SI 3 "immediate_operand" "i")))]
++ (match_operand:SI 3 "const_0_to_255_operand" "N")))]
+ "TARGET_SSE2"
+ "pinsrw\t{%3, %2, %0|%0, %2, %3}"
+ [(set_attr "type" "ssecvt")
+@@ -22935,7 +22970,7 @@
+ (zero_extend:SI
+ (vec_select:HI (match_operand:V8HI 1 "register_operand" "x")
+ (parallel
+- [(match_operand:SI 2 "immediate_operand" "i")]))))]
++ [(match_operand:SI 2 "const_0_to_7_operand" "N")]))))]
+ "TARGET_SSE2"
+ "pextrw\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "type" "ssecvt")
================================================================
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