commit 9612faf95140554c1c3a0a8fa8d26dc903da9a7f
Author: Jakub Bogusz <[email protected]>
Date:   Sun Jul 17 20:02:05 2016 +0200

    - pl

 sigrok-firmware-saleae-logic16.spec | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)
---
diff --git a/sigrok-firmware-saleae-logic16.spec 
b/sigrok-firmware-saleae-logic16.spec
index 0cd4b23..f1b90dc 100644
--- a/sigrok-firmware-saleae-logic16.spec
+++ b/sigrok-firmware-saleae-logic16.spec
@@ -1,10 +1,10 @@
 Summary:       Firmware for Saleae Logic16 logic analyzer
+Summary(pl.UTF-8):     Firmware dla analizatora stanów logicznych Saleae 
Logic16
 Name:          sigrok-firmware-saleae-logic16
 Version:       1.1.15
 Release:       1
 License:       Unknown
 Group:         Applications/Engineering
-URL:           http://sigrok.org/wiki/Saleae_Logic16
 Source0:       http://downloads.saleae.com/Logic%20%{version}%20(64-bit).zip
 # NoSource0-md5:       6d91d1decac041dc29405379af530261
 NoSource:      0
@@ -12,6 +12,7 @@ Source1:      
http://sigrok.org/gitweb/?p=sigrok-util.git;a=blob_plain;f=firmware/sal
 # Source1-md5: c69f130ea7f4ac86219737ad4f6b9dc0
 Source2:       
http://sigrok.org/gitweb/?p=sigrok-util.git;a=blob_plain;f=firmware/saleae-logic16/parseelf.py;hb=HEAD;/parseelf.py
 # Source2-md5: ee0323c709a7cc8828f4806988b45e85
+URL:           http://sigrok.org/wiki/Saleae_Logic16
 BuildRequires: python3
 BuildRequires: unzip
 BuildArch:     noarch
@@ -19,20 +20,24 @@ BuildRoot:  %{tmpdir}/%{name}-%{version}-root-%(id -u -n)
 
 %description
 Firmware for The Saleae Logic16 - a USB-based, 16-channel logic
-analyzer with 100/50/32/16MHz sampling rate (at 3/6/9/16 enabled
+analyzer with 100/50/32/16 MHz sampling rate (at 3/6/9/16 enabled
 channels).
 
+%description
+Firmware dla urządzenia Saleae Logic16 - opartego na USB,
+16-kanałowego analizatora stanów logicznych z częstotliwością
+próbkowania 100/50/32/16 MHz (przy 3/6/9/16 włączonych kanałach).
+
 %prep
 %setup -q -n "Logic %{version} (64-bit)"
 install %{SOURCE1} sigrok-fwextract-saleae-logic16
 install %{SOURCE2} parseelf.py
 
 %build
-python3 sigrok-fwextract-saleae-logic16 Logic
+%{__python3} sigrok-fwextract-saleae-logic16 Logic
 
 %install
 rm -rf $RPM_BUILD_ROOT
-
 install -d $RPM_BUILD_ROOT%{_datadir}/sigrok-firmware
 
 install saleae-logic16-fx2.fw saleae-logic16-fpga-18.bitstream 
saleae-logic16-fpga-33.bitstream \
================================================================

---- gitweb:

http://git.pld-linux.org/gitweb.cgi/packages/sigrok-firmware-saleae-logic16.git/commitdiff/9612faf95140554c1c3a0a8fa8d26dc903da9a7f

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