Here's a patch which converts most of the c++ comments in C files into
c-style ones. I didn't change anything in the bios or bochs directories.
--Josh
--
Josh Wilmes ([EMAIL PROTECTED]) | http://www.hitchhiker.org
Index: guest/virtcode/helper.c
===================================================================
RCS file: /cvsroot-plex86/plex86/guest/virtcode/helper.c,v
retrieving revision 1.2
diff -r1.2 helper.c
42c42
< vidmem[cursor++] = text[i++] | 0x0700; // 0x0f00 for bold
---
> vidmem[cursor++] = text[i++] | 0x0700; /* 0x0f00 for bold */
57c57
< vidmem[cursor++] = c | 0x0700; // 0x0f00 for bold;
---
> vidmem[cursor++] = c | 0x0700; /* 0x0f00 for bold; */
Index: kernel/host-all.c
===================================================================
RCS file: /cvsroot-plex86/plex86/kernel/host-all.c,v
retrieving revision 1.14
diff -r1.14 host-all.c
289,291c289,293
<
< //if (vm->log_buffer_info.event && !vm->log_buffer_info.locked)
< // host_print_buf(vm);
---
>
> /*
> if (vm->log_buffer_info.event && !vm->log_buffer_info.locked)
> host_print_buf(vm);
> */
304,305c306,309
< //if (vm->log_buffer_info.event && !vm->log_buffer_info.locked)
< // host_print_buf(vm);
---
> /*
> if (vm->log_buffer_info.event && !vm->log_buffer_info.locked)
> host_print_buf(vm);
> */
Index: kernel/mon-paging.c
===================================================================
RCS file: /cvsroot-plex86/plex86/kernel/mon-paging.c,v
retrieving revision 1.3
diff -r1.3 mon-paging.c
202c202
< //getPageUsage(vm, ppi);
---
> /* getPageUsage(vm, ppi); */
240,241c240,242
< //monprint(vm, "strengthenPP: bl=0x%x, AP=%u\n",
< //pusage->attr.fields.laddr_backlink, new_access_perm);
---
> /*
> monprint(vm, "strengthenPP: bl=0x%x, AP=%u\n",
> pusage->attr.fields.laddr_backlink, new_access_perm);
243c244,245
< //monpanic(vm, "strengthenPP: monPTE.P==0\n");
---
> monpanic(vm, "strengthenPP: monPTE.P==0\n");
> */
661,664c663,668
< //monprint(vm, "PDE.base=0x%x CR3=0x%x\n",
< // A20PageIndex(vm, guestPDE.fields.base),
< // A20Addr(vm, vm->guest_cpu.cr3));
< return(MapLinEmulate);
---
> /*
> monprint(vm, "PDE.base=0x%x CR3=0x%x\n",
> A20PageIndex(vm, guestPDE.fields.base),
> A20Addr(vm, vm->guest_cpu.cr3));
> */
> return(MapLinEmulate);
Index: kernel/emulation/ctrl_xfer_pro.c
===================================================================
RCS file: /cvsroot-plex86/plex86/kernel/emulation/ctrl_xfer_pro.c,v
retrieving revision 1.5
diff -r1.5 ctrl_xfer_pro.c
800,801c800,801
< // check new CS selector index within its descriptor limits,
< // else #GP(new CS selector)
---
> /* check new CS selector index within its descriptor limits,
> * else #GP(new CS selector) */
805c805
< // examine AR byte of selected descriptor for various legal values
---
> /* examine AR byte of selected descriptor for various legal values */
811c811
< if (cs_cache.desc.type & D_S) { // normal segment
---
> if (cs_cache.desc.type & D_S) { /* normal segment */
848c848
< // stack must be big enough for return addr, else #SS(0)
---
> /* stack must be big enough for return addr, else #SS(0) */
855c855
< // IP must be in code seg limit, else #GP(0)
---
> /* IP must be in code seg limit, else #GP(0) */
862c862
< // push return address onto stack (CS padded to 32bits)
---
> /* push return address onto stack (CS padded to 32bits) */
866c866
< else { // 16bit opsize
---
> else { /* 16bit opsize */
872c872
< // IP must be in code seg limit, else #GP(0)
---
> /* IP must be in code seg limit, else #GP(0) */
893c893
< else { // gate & special segment
---
> else { /* gate & special segment */
906,908c906,908
< case 1: // available 16bit TSS
< case 9: // available 32bit TSS
< // TSS DPL must be >= CPL, else #TS(TSS selector)
---
> case 1: /* available 16bit TSS */
> case 9: /* available 32bit TSS */
> /* TSS DPL must be >= CPL, else #TS(TSS selector) */
914c914
< // TSS DPL must be >= TSS selector RPL, else #TS(TSS selector)
---
> /* TSS DPL must be >= TSS selector RPL, else #TS(TSS selector) */
920,922c920,926
< // descriptor AR byte must specify available TSS,
< // else #TS(TSS selector) */
< // this is taken care of by the 'default' case of switch statement */
---
> /* descriptor AR byte must specify available TSS,
> * else #TS(TSS selector)
> * this is taken care of by the 'default' case of switch statement
> *
> * Task State Seg must be present, else #NP(TSS selector)
> * checked in task_switch()
> */
924,927c928
< // Task State Seg must be present, else #NP(TSS selector)
< // checked in task_switch()
<
< // SWITCH_TASKS _without_ nesting to TSS
---
> /* SWITCH_TASKS _without_ nesting to TSS */
930c931
< // IP must be in code seg limit, else #TS(0)
---
> /* IP must be in code seg limit, else #TS(0) */
938,940c939,943
< case 5: // TASK GATE
< //bx_printf("call_pro: task gate\n");
< // gate descriptor DPL must be >= CPL else #TS(gate selector)
---
> case 5: /* TASK GATE */
> /*
> bx_printf("call_pro: task gate\n");
> gate descriptor DPL must be >= CPL else #TS(gate selector)
> */
947,948c950,953
< // gate descriptor DPL must be >= gate selector RPL
< // else #TS(gate selector)
---
> /*
> gate descriptor DPL must be >= gate selector RPL
> else #TS(gate selector)
> */
955c960
< // task gate must be present else #NP(gate selector)
---
> /* task gate must be present else #NP(gate selector) */
962,964c967,969
< // examine selector to TSS, given in Task Gate descriptor
< // must specify global in the local/global bit else #TS(TSS selector)
<
---
> /* examine selector to TSS, given in Task Gate descriptor
> * must specify global in the local/global bit else #TS(TSS selector)
> */
973c978
< // index must be within GDT limits else #TS(TSS selector)
---
> /* index must be within GDT limits else #TS(TSS selector) */
977,978c982,984
< // descriptor AR byte must specify available TSS
< // else #TS(TSS selector)
---
> /* descriptor AR byte must specify available TSS
> * else #TS(TSS selector)
> */
990c996
< // task state segment must be present, else #NP(tss selector)
---
> /* task state segment must be present, else #NP(tss selector) */
996c1002
< // SWITCH_TASKS without nesting to TSS
---
> /* SWITCH_TASKS without nesting to TSS */
1000c1006
< // eIP must be within code segment limit, else #TS(0)
---
> /* eIP must be within code segment limit, else #TS(0) */
1013,1018c1019,1026
< case 4: // 16bit CALL GATE
< case 12: // 32bit CALL GATE
< //if (gate_descriptor.type==4)
< // bx_printf("CALL: 16bit call gate\n");
< //else
< // bx_printf("CALL: 32bit call gate\n");
---
> case 4: /* 16bit CALL GATE */
> case 12: /* 32bit CALL GATE */
> /*
> if (gate_descriptor.type==4)
> bx_printf("CALL: 16bit call gate\n");
> else
> bx_printf("CALL: 32bit call gate\n");
> */
1020,1021c1028,1029
< // call gate DPL must be >= CPL, else #GP(call gate selector)
< // call gate DPL must be >= RPL, else #GP(call gate selector)
---
> /* call gate DPL must be >= CPL, else #GP(call gate selector) */
> /* call gate DPL must be >= RPL, else #GP(call gate selector) */
1028c1036
< // call gate must be present, else #NP(call gate selector)
---
> /* call gate must be present, else #NP(call gate selector) */
1034c1042
< // examine code segment selector in call gate descriptor
---
> /* examine code segment selector in call gate descriptor */
1045c1053
< // selector must not be null else #GP(0)
---
> /* selector must not be null else #GP(0) */
1053,1054c1061,1062
< // selector must be within its descriptor table limits,
< // else #GP(code segment selector)
---
> /* selector must be within its descriptor table limits,
> * else #GP(code segment selector) */
1059,1062c1067,1071
< // AR byte of selected descriptor must indicate code segment,
< // else #GP(code segment selector)
< // DPL of selected descriptor must be <= CPL,
< // else #GP(code segment selector)
---
> /* AR byte of selected descriptor must indicate code segment,
> * else #GP(code segment selector)
> * DPL of selected descriptor must be <= CPL,
> * else #GP(code segment selector)
> */
1071,1073c1080,1083
< // CALL GATE TO MORE PRIVILEGE
< // if non-conforming code segment and DPL < CPL then
< // ??? use gate_descriptor.dpl or cs_descriptor.dpl ???
---
> /* CALL GATE TO MORE PRIVILEGE
> * if non-conforming code segment and DPL < CPL then
> * ??? use gate_descriptor.dpl or cs_descriptor.dpl ???
> */
1091c1101
< //bx_printf("CALL: Call Gate: to more priviliged level\n");
---
> /* bx_printf("CALL: Call Gate: to more priviliged level\n"); */
1093c1103
< // get new SS selector for new privilege level from TSS
---
> /* get new SS selector for new privilege level from TSS */
1099,1100c1109,1111
< // check selector & descriptor for new SS:
< // selector must not be null, else #TS(0)
---
> /* check selector & descriptor for new SS:
> * selector must not be null, else #TS(0)
> */
1107,1108c1118,1120
< // selector index must be within its descriptor table limits,
< // else #TS(SS selector)
---
> /* selector index must be within its descriptor table limits,
> * else #TS(SS selector)
> */
1115,1116c1127,1129
< // selector's RPL must equal DPL of code segment,
< // else #TS(SS selector)
---
> /* selector's RPL must equal DPL of code segment,
> * else #TS(SS selector)
> */
1123,1124c1136,1138
< // stack segment DPL must equal DPL of code segment,
< // else #TS(SS selector)
---
> /* stack segment DPL must equal DPL of code segment,
> * else #TS(SS selector)
> */
1131,1132c1145,1147
< // descriptor must indicate writable data segment,
< // else #TS(SS selector)
---
> /* descriptor must indicate writable data segment,
> * else #TS(SS selector)
> */
1142c1157
< // segment must be present, else #SS(SS selector)
---
> /* segment must be present, else #SS(SS selector) */
1150c1165
< // new stack must have room for parameters plus 16 bytes
---
> /* new stack must have room for parameters plus 16 bytes */
1153c1168
< // new stack must have room for parameters plus 8 bytes
---
> /* new stack must have room for parameters plus 8 bytes */
1157c1172
< // get word count from call gate, mask to 5 bits
---
> /* get word count from call gate, mask to 5 bits */
1162c1177
< // get word count from call gate, mask to 5 bits
---
> /* get word count from call gate, mask to 5 bits */
1167,1168c1182,1184
< // new stack must have room for parameters plus return info
< // else #SS(SS selector)
---
> /* new stack must have room for parameters plus return info
> * else #SS(SS selector)
> */
1176c1192
< // new eIP must be in code segment limit else #GP(0)
---
> /* new eIP must be in code segment limit else #GP(0) */
1184c1200
< // save return SS:eSP to be pushed on new stack
---
> /* save return SS:eSP to be pushed on new stack */
1192c1208
< // save return CS:eIP to be pushed on new stack
---
> /* save return CS:eIP to be pushed on new stack */
1228c1244
< // push pointer of old stack onto new stack
---
> /* push pointer of old stack onto new stack */
1248,1249c1264,1267
< //access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + i*2,
< // 2, 0, BX_WRITE, ¶meter_word[i]);
---
> /*
> access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + i*2,
> 2, 0, BX_WRITE, ¶meter_word[i]);
> */
1255,1256c1273,1276
< //access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + i*4,
< // 4, 0, BX_WRITE, ¶meter_dword[i]);
---
> /*
> access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + i*4,
> 4, 0, BX_WRITE, ¶meter_dword[i]);
> */
1260c1280
< // push return address onto new stack
---
> /* push return address onto new stack */
1273c1293
< // CALL GATE TO SAME PRIVILEGE
---
> /* CALL GATE TO SAME PRIVILEGE */
1277c1297
< //bx_printf("CALL: Call Gate: to same priviliged level\n");
---
> /*bx_printf("CALL: Call Gate: to same priviliged level\n"); */
1284,1286c1304,1307
< //if (i->os_32) {}
< // stack must room for 8-byte return address (2 are padding)
< // else #SS(0)
---
> /*if (i->os_32) {}
> * stack must room for 8-byte return address (2 are padding)
> * else #SS(0)
> */
1293,1294c1314,1316
< // stack must room for 4-byte return address
< // else #SS(0)
---
> /* stack must room for 4-byte return address
> * else #SS(0)
> */
1301c1323
< // EIP must be within code segment limit, else #GP(0)
---
> /* EIP must be within code segment limit, else #GP(0) */
1308c1330
< // push return address onto stack
---
> /* push return address onto stack */
1313c1335
< // push return address onto stack
---
> /* push return address onto stack */
1318,1320c1340,1343
< // load CS:EIP from gate
< // load code segment descriptor into CS register
< // set RPL of CS to CPL
---
> /* load CS:EIP from gate
> * load code segment descriptor into CS register
> * set RPL of CS to CPL
> */
1393c1416
< // return selector RPL must be >= CPL, else #GP(return selector)
---
> /* return selector RPL must be >= CPL, else #GP(return selector) */
1403,1404c1426,1428
< // if return selector RPL == CPL then
< // RETURN TO SAME LEVEL
---
> /* if return selector RPL == CPL then
> * RETURN TO SAME LEVEL
> */
1406c1430
< // return selector must be non-null, else #GP(0)
---
> /* return selector must be non-null, else #GP(0) */
1412,1413c1436,1438
< // selector index must be within its descriptor table limits,
< // else #GP(selector)
---
> /* selector index must be within its descriptor table limits,
> * else #GP(selector)
> */
1417c1442
< // descriptor AR byte must indicate code segment, else #GP(selector)
---
> /* descriptor AR byte must indicate code segment, else #GP(selector) */
1425,1426c1450,1452
< // if non-conforming then code segment DPL must = CPL,
< // else #GP(selector)
---
> /* if non-conforming then code segment DPL must = CPL,
> * else #GP(selector)
> */
1433,1434c1459,1461
< // if conforming then code segment DPL must be <= CPL,
< // else #GP(selector)
---
> /* if conforming then code segment DPL must be <= CPL,
> * else #GP(selector)
> */
1441c1468
< // code segment must be present, else #NP(selector)
---
> /* code segment must be present, else #NP(selector) */
1447c1474
< // top word on stack must be within stack limits, else #SS(0)
---
> /* top word on stack must be within stack limits, else #SS(0) */
1453c1480
< // eIP must be in code segment limit, else #GP(0)
---
> /* eIP must be in code segment limit, else #GP(0) */
1469,1471c1496,1499
< // load CS:eIP from stack
< // load CS register with descriptor
< // increment eSP
---
> /* load CS:eIP from stack
> * load CS register with descriptor
> * increment eSP
> */
1499,1501c1527,1530
< //bx_printf("return: to outer level %04x:%08x\n",
< // BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
< // BX_CPU_THIS_PTR prev_eip);
---
> /*bx_printf("return: to outer level %04x:%08x\n",
> * BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
> * BX_CPU_THIS_PTR prev_eip);
> */
Index: kernel/emulation/proc_ctrl.c
===================================================================
RCS file: /cvsroot-plex86/plex86/kernel/emulation/proc_ctrl.c,v
retrieving revision 1.7
diff -r1.7 proc_ctrl.c
85c85
< WriteReg32(vm, vm->i.rm, msw); // zeros out high 16bits
---
> WriteReg32(vm, vm->i.rm, msw); /* zeros out high 16bits */
Index: kernel/emulation/protect_ctrl.c
===================================================================
RCS file: /cvsroot-plex86/plex86/kernel/emulation/protect_ctrl.c,v
retrieving revision 1.4
diff -r1.4 protect_ctrl.c
48,49c48,49
< // if 32bit opsize, then 0xff3f is or'd into
< // upper 16bits of register
---
> /* if 32bit opsize, then 0xff3f is or'd into
> * upper 16bits of register */
71c71
< // ARPL not recognized in real or v8086 mode
---
> /* ARPL not recognized in real or v8086 mode */
466c466
< if ( (dword2 & 0x00001000) == 0 ) { // system segment
---
> if ( (dword2 & 0x00001000) == 0 ) { /* system segment */
471,475c471,475
< case 1: // 16bit TSS
< case 3: // 16bit TSS
< case 2: // LDT
< case 9: // 32bit TSS G00A
< case 11:// 32bit TSS G00A
---
> case 1: /* 16bit TSS */
> case 3: /* 16bit TSS */
> case 2: /* LDT */
> case 9: /* 32bit TSS G00A */
> case 11:/* 32bit TSS G00A */
491c491
< else { // data & code segment
---
> else { /* data & code segment */
496c496
< // conforming code segment, no check done
---
> /* conforming code segment, no check done */
515c515
< // chop off upper 16 bits
---
> /* chop off upper 16 bits */
Index: kernel/emulation/segment_pro.c
===================================================================
RCS file: /cvsroot-plex86/plex86/kernel/emulation/segment_pro.c,v
retrieving revision 1.5
diff -r1.5 segment_pro.c
355,356c355,358
< // SET_DESCRIPTOR(vm->guest_cpu.desc_cache[sreg].desc,
< // base, limit, 0, 0, 0, 1, dpl, D_CODE | D_WRITE | D_ACCESSED)
---
> /*
> SET_DESCRIPTOR(vm->guest_cpu.desc_cache[sreg].desc,
> base, limit, 0, 0, 0, 1, dpl, D_CODE | D_WRITE | D_ACCESSED)
> */
362,363c364,367
< // SET_DESCRIPTOR(vm->guest_cpu.desc_cache[sreg].desc,
< // base, limit, 0, 0, 0, 1, dpl, D_DATA | D_WRITE | D_ACCESSED)
---
> /*
> SET_DESCRIPTOR(vm->guest_cpu.desc_cache[sreg].desc,
> base, limit, 0, 0, 0, 1, dpl, D_DATA | D_WRITE | D_ACCESSED)
> */
Index: kernel/emulation/stack.c
===================================================================
RCS file: /cvsroot-plex86/plex86/kernel/emulation/stack.c,v
retrieving revision 1.4
diff -r1.4 stack.c
287,290c287,292
< //if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b && vm->i.os_32==0) {
< // bx_printf("enter(): stacksize!=opsize: I'm unsure of the code for this\n");
< // bx_panic(" The Intel manuals are a mess on this one!\n");
< // }
---
> /*
> if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b && vm->i.os_32==0) {
> bx_printf("enter(): stacksize!=opsize: I'm unsure of the code for this\n");
> bx_panic(" The Intel manuals are a mess on this one!\n");
> }
> */
Index: kernel/emulation/tasking.c
===================================================================
RCS file: /cvsroot-plex86/plex86/kernel/emulation/tasking.c,v
retrieving revision 1.3
diff -r1.3 tasking.c
34,124c34,125
< // Notes:
< // ======
< // Step 2: TSS descriptor is not busy TS (for IRET); GP (for JMP, CALL, INT)
< // returns error code (Task's backlink TSS)???
<
< // * TSS selector must map to GDT
< // * TSS is stored in linear address space
< // * what to do with I/O Map Base
< // * what to do with T flag
< // * where to set CR3 and flush paging cache
< // * what happens when fault occurs, with some seg regs having valid bit cleared?
< // * should check validity of current TR(TSS) before writing into it
< //
<
< // ======================
< // 286 Task State Segment
< // ======================
< // dynamic item | hex dec offset
< // 0 task LDT selector | 2a 42
< // 1 DS selector | 28 40
< // 1 SS selector | 26 38
< // 1 CS selector | 24 36
< // 1 ES selector | 22 34
< // 1 DI | 20 32
< // 1 SI | 1e 30
< // 1 BP | 1c 28
< // 1 SP | 1a 26
< // 1 BX | 18 24
< // 1 DX | 16 22
< // 1 CX | 14 20
< // 1 AX | 12 18
< // 1 flag word | 10 16
< // 1 IP (entry point) | 0e 14
< // 0 SS for CPL 2 | 0c 12
< // 0 SP for CPL 2 | 0a 10
< // 0 SS for CPL 1 | 08 08
< // 0 SP for CPL 1 | 06 06
< // 0 SS for CPL 0 | 04 04
< // 0 SP for CPL 0 | 02 02
< // back link selector to TSS | 00 00
<
<
< // ======================
< // 386 Task State Segment
< // ======================
< // |31 16|15 0|
< // |I/O Map Base |000000000000000000000|T| 64 static
< // |0000000000000000| LDT | 60 static
< // |0000000000000000| GS selector | 5c dynamic
< // |0000000000000000| FS selector | 58 dynamic
< // |0000000000000000| DS selector | 54 dynamic
< // |0000000000000000| SS selector | 50 dynamic
< // |0000000000000000| CS selector | 4c dynamic
< // |0000000000000000| ES selector | 48 dynamic
< // | EDI | 44 dynamic
< // | ESI | 40 dynamic
< // | EBP | 3c dynamic
< // | ESP | 38 dynamic
< // | EBX | 34 dynamic
< // | EDX | 30 dynamic
< // | ECX | 2c dynamic
< // | EAX | 28 dynamic
< // | EFLAGS | 24 dynamic
< // | EIP (entry point) | 20 dynamic
< // | CR3 (PDPR) | 1c static
< // |000000000000000 | SS for CPL 2 | 18 static
< // | ESP for CPL 2 | 14 static
< // |000000000000000 | SS for CPL 1 | 10 static
< // | ESP for CPL 1 | 0c static
< // |000000000000000 | SS for CPL 0 | 08 static
< // | ESP for CPL 0 | 04 static
< // |000000000000000 | back link to prev TSS | 00 dynamic (updated only when return expected)
<
<
< // ==================================================
< // Effect of task switch on Busy, NT, and Link Fields
< // ==================================================
<
< // Field jump call/interrupt iret
< // ------------------------------------------------------
< // new busy bit Set Set No change
< // old busy bit Cleared No change Cleared
< // new NT flag No change Set No change
< // old NT flag No change No change Cleared
< // new link No change old TSS selector No change
< // old link No change No change No change
< // CR0.TS Set Set Set
<
< // Note: I checked 386, 486, and Pentium, and they all exhibited
< // exactly the same behaviour as above. There seems to
< // be some misprints in the Intel docs.
---
> /* Notes:
> * ======
> * Step 2: TSS descriptor is not busy TS (for IRET); GP (for JMP, CALL, INT)
> * returns error code (Task's backlink TSS)???
> *
> * * TSS selector must map to GDT
> * * TSS is stored in linear address space
> * * what to do with I/O Map Base
> * * what to do with T flag
> * * where to set CR3 and flush paging cache
> * * what happens when fault occurs, with some seg regs having valid bit cleared?
> * * should check validity of current TR(TSS) before writing into it
> *
> *
> * ======================
> * 286 Task State Segment
> * ======================
> * dynamic item | hex dec offset
> * 0 task LDT selector | 2a 42
> * 1 DS selector | 28 40
> * 1 SS selector | 26 38
> * 1 CS selector | 24 36
> * 1 ES selector | 22 34
> * 1 DI | 20 32
> * 1 SI | 1e 30
> * 1 BP | 1c 28
> * 1 SP | 1a 26
> * 1 BX | 18 24
> * 1 DX | 16 22
> * 1 CX | 14 20
> * 1 AX | 12 18
> * 1 flag word | 10 16
> * 1 IP (entry point) | 0e 14
> * 0 SS for CPL 2 | 0c 12
> * 0 SP for CPL 2 | 0a 10
> * 0 SS for CPL 1 | 08 08
> * 0 SP for CPL 1 | 06 06
> * 0 SS for CPL 0 | 04 04
> * 0 SP for CPL 0 | 02 02
> * back link selector to TSS | 00 00
> *
> *
> * ======================
> * 386 Task State Segment
> * ======================
> * |31 16|15 0|
> * |I/O Map Base |000000000000000000000|T| 64 static
> * |0000000000000000| LDT | 60 static
> * |0000000000000000| GS selector | 5c dynamic
> * |0000000000000000| FS selector | 58 dynamic
> * |0000000000000000| DS selector | 54 dynamic
> * |0000000000000000| SS selector | 50 dynamic
> * |0000000000000000| CS selector | 4c dynamic
> * |0000000000000000| ES selector | 48 dynamic
> * | EDI | 44 dynamic
> * | ESI | 40 dynamic
> * | EBP | 3c dynamic
> * | ESP | 38 dynamic
> * | EBX | 34 dynamic
> * | EDX | 30 dynamic
> * | ECX | 2c dynamic
> * | EAX | 28 dynamic
> * | EFLAGS | 24 dynamic
> * | EIP (entry point) | 20 dynamic
> * | CR3 (PDPR) | 1c static
> * |000000000000000 | SS for CPL 2 | 18 static
> * | ESP for CPL 2 | 14 static
> * |000000000000000 | SS for CPL 1 | 10 static
> * | ESP for CPL 1 | 0c static
> * |000000000000000 | SS for CPL 0 | 08 static
> * | ESP for CPL 0 | 04 static
> * |000000000000000 | back link to prev TSS | 00 dynamic (updated only when return expected)
> *
> *
> * ==================================================
> * Effect of task switch on Busy, NT, and Link Fields
> * ==================================================
> *
> * Field jump call/interrupt iret
> * ------------------------------------------------------
> * new busy bit Set Set No change
> * old busy bit Cleared No change Cleared
> * new NT flag No change Set No change
> * old NT flag No change No change Cleared
> * new link No change old TSS selector No change
> * old link No change No change No change
> * CR0.TS Set Set Set
> *
> * Note: I checked 386, 486, and Pentium, and they all exhibited
> * exactly the same behaviour as above. There seems to
> * be some misprints in the Intel docs.
> */
309c310
< //exception(ExceptionTS, tss_selector->value & 0xfffc, 0);
---
> /* exception(ExceptionTS, tss_selector->value & 0xfffc, 0); */
697c698
< // +++
---
> /* +++ */
Index: kernel/emulation/vm8086.c
===================================================================
RCS file: /cvsroot-plex86/plex86/kernel/emulation/vm8086.c,v
retrieving revision 1.2
diff -r1.2 vm8086.c
43,56c43,58
< // Must be 32bit effective opsize, VM is in upper 16bits of eFLAGS
< // CPL = 0 to get here
<
< // ----------------
< // | | OLD GS | eSP+32
< // | | OLD FS | eSP+28
< // | | OLD DS | eSP+24
< // | | OLD ES | eSP+20
< // | | OLD SS | eSP+16
< // | OLD ESP | eSP+12
< // | OLD EFLAGS | eSP+8
< // | | OLD CS | eSP+4
< // | OLD EIP | eSP+0
< // ----------------
---
> /*
> * Must be 32bit effective opsize, VM is in upper 16bits of eFLAGS
> * CPL = 0 to get here
> *
> * ----------------
> * | | OLD GS | eSP+32
> * | | OLD FS | eSP+28
> * | | OLD DS | eSP+24
> * | | OLD ES | eSP+20
> * | | OLD SS | eSP+16
> * | OLD ESP | eSP+12
> * | OLD EFLAGS | eSP+8
> * | | OLD CS | eSP+4
> * | OLD EIP | eSP+0
> * ----------------
> */
63c65
< // top 36 bytes of stack must be within stack limits, else #GP(0)
---
> /* top 36 bytes of stack must be within stack limits, else #GP(0) */
76c78
< // load SS:ESP from stack
---
> /* load SS:ESP from stack */
80c82
< // load ES,DS,FS,GS from stack
---
> /* load ES,DS,FS,GS from stack */
91c93
< // load CS:EIP from stack; already read and passed as args
---
> /* load CS:EIP from stack; already read and passed as args */
99c101
< G_ESP(vm) = new_esp; // Full 32bits are loaded.
---
> G_ESP(vm) = new_esp; /* Full 32bits are loaded. */
Index: user/cosim.c
===================================================================
RCS file: /cvsroot-plex86/plex86/user/cosim.c,v
retrieving revision 1.6
diff -r1.6 cosim.c
40c40
< //#define RunMethod RunGuestNMethodEmulate
---
> /* #define RunMethod RunGuestNMethodEmulate */
481,482c481,484
< //time_elapsed_t *time_elapsed = (time_elapsed_t *) user_msgs.msg;
< //plugin_call_elapsed(time_elapsed->elapsed);
---
> /*
> time_elapsed_t *time_elapsed = (time_elapsed_t *) user_msgs.msg;
> plugin_call_elapsed(time_elapsed->elapsed);
> */
Index: user/user.c
===================================================================
RCS file: /cvsroot-plex86/plex86/user/user.c,v
retrieving revision 1.17
diff -r1.17 user.c
41,42c41,42
< //#define RunMethod RunGuestNMethodBreakpoint // OK solo with tick hacks
< //#define RunMethod RunGuestNMethodEmulate // OK solo with tick hacks
---
> //#define RunMethod RunGuestNMethodBreakpoint /* OK solo with tick hacks */
> //#define RunMethod RunGuestNMethodEmulate /* OK solo with tick hacks */
Index: user/plugins/loader/bin.c
===================================================================
RCS file: /cvsroot-plex86/plex86/user/plugins/loader/bin.c,v
retrieving revision 1.2
diff -r1.2 bin.c
170c170
< // read in ROM BIOS image file
---
> /* read in ROM BIOS image file */
211c211
< // +++ fix this wierdness
---
> /* +++ fix this wierdness */
Index: user/plugins/loader/hack-linux.c
===================================================================
RCS file: /cvsroot-plex86/plex86/user/plugins/loader/hack-linux.c,v
retrieving revision 1.1
diff -r1.1 hack-linux.c
121c121
< return 0; // OK
---
> return 0; /* OK */
128c128
< // Set fields in a guest_cpu_t structure to RESET values
---
> /* Set fields in a guest_cpu_t structure to RESET values */
131,133c131,133
< // General Registers
< cpu->eax = 0; // processor tests passed
< cpu->ebx = 0; // +++
---
> /* General Registers */
> cpu->eax = 0; /* processor tests passed */
> cpu->ebx = 0; /* +++ */
140c140
< cpu->eflags = 0x00000002; // only reserved bit set
---
> cpu->eflags = 0x00000002; /* only reserved bit set */
143c143
< // CS
---
> /* CS */
148c148
< cpu->cs.des.type = 0x1A; // execute/read
---
> cpu->cs.des.type = 0x1A; /* execute/read */
159c159
< // DS
---
> /* DS */
164c164
< cpu->ds.des.type = 0x12; // data seg, RW
---
> cpu->ds.des.type = 0x12; /* data seg, RW */
175c175
< // Copy DS to other data segments
---
> /* Copy DS to other data segments */
181c181
< // LDTR
---
> /* LDTR */
183c183
< // +++ check out Table 8-1
---
> /* +++ check out Table 8-1 */
186c186
< // TR
---
> /* TR */
188c188
< // +++ check out Table 8-1
---
> /* +++ check out Table 8-1 */
191c191
< // GDTR
---
> /* GDTR */
195c195
< // IDTR
---
> /* IDTR */
197c197
< // +++ check out Table 8-1
---
> /* +++ check out Table 8-1 */
200c200
< // Debug Registers
---
> /* Debug Registers */
218c218
< // Test Registers
---
> /* Test Registers */
225,226c225,226
< // Control Registers
< // +++ CR0 reset: CD/NW unchanged, bit4 set, other cleared
---
> /* Control Registers
> * +++ CR0 reset: CD/NW unchanged, bit4 set, other cleared */
240c240
< // Set fields in a guest_cpu_t structure to RESET values
---
> /* Set fields in a guest_cpu_t structure to RESET values */
243,245c243,245
< // General Registers
< cpu->eax = 0; // processor tests passed
< cpu->ebx = 0; // +++
---
> /* General Registers */
> cpu->eax = 0; /* processor tests passed */
> cpu->ebx = 0; /* +++ */
252c252
< cpu->eflags = 0x00000002; // only reserved bit set
---
> cpu->eflags = 0x00000002; /* only reserved bit set */
255c255
< // CS
---
> /* CS */
260c260
< cpu->cs.des.type = 0x1A; // execute/read
---
> cpu->cs.des.type = 0x1A; /* execute/read */
271c271
< // DS
---
> /* DS */
276c276
< cpu->ds.des.type = 0x12; // data seg, RW
---
> cpu->ds.des.type = 0x12; /* data seg, RW */
287c287
< // Copy DS to other data segments
---
> /* Copy DS to other data segments */
293c293
< // LDTR
---
> /* LDTR */
295c295
< // +++ check out Table 8-1
---
> /* +++ check out Table 8-1 */
298c298
< // TR
---
> /* TR */
300c300
< // +++ check out Table 8-1
---
> /* +++ check out Table 8-1
303c303
< // GDTR
---
> /* GDTR */
305c305
< // +++ check out Table 8-1
---
> /* +++ check out Table 8-1 */
308c308
< // IDTR
---
> /* IDTR */
310c310
< // +++ check out Table 8-1
---
> /* +++ check out Table 8-1 */
313c313
< // Debug Registers
---
> /* Debug Registers */
331c331
< // Test Registers
---
> /* Test Registers */
338,339c338,339
< // Control Registers
< // +++ CR0 reset: CD/NW unchanged, bit4 set, other cleared
---
> /* Control Registers
> * +++ CR0 reset: CD/NW unchanged, bit4 set, other cleared */
Index: user/plugins/loader/kernel.c
===================================================================
RCS file: /cvsroot-plex86/plex86/user/plugins/loader/kernel.c,v
retrieving revision 1.1
diff -r1.1 kernel.c
55c55
< // Get the file= parameter
---
> /* Get the file= parameter */
62,64c62,64
< // ============================
< // Get the [address=] parameter
< // ============================
---
> /* ============================ *
> * Get the [address=] parameter *
> * ============================ */
74,76c74,76
< // ==========================
< // Get the [stack=] parameter
< // ==========================
---
> /* ========================== *
> * Get the [stack=] parameter *
> * ========================== */
83,85c83,85
< // ===================================
< // Get the [rd=address:path] parameter
< // ===================================
---
> /* =================================== *
> * Get the [rd=address:path] parameter *
> * =================================== */
111,113c111,113
< // ===========================
< // Get the [hack=os] parameter
< // ===========================
---
> /* =========================== *
> * Get the [hack=os] parameter *
> * =========================== */
Index: user/plugins/misc/replay.c
===================================================================
RCS file: /cvsroot-plex86/plex86/user/plugins/misc/replay.c,v
retrieving revision 1.2
diff -r1.2 replay.c
52c52
< // Get the file= parameter
---
> /* Get the file= parameter */
