http://realworldtech.com/forums/index.cfm?action=detail&id=80552&threadid=80534&roomid=2
<quip> I'd say: "Totally insignificant". The biggest problem is that Intel should just have documented the TLB behavior better. The Core 2 changes are kind of gray area, and the old documentation simply didn't talk about the higher-level page table structures and the caching rules for them. So that part is just a good clarification, and while it could be called a "bug" just because older CPU's didn't do that caching, I don't think it's an errata per se. Of course, if you depended on it not happening (and a lot of people did), it's painful. But it really does make the architecture definition better and clearer. (I don't think Linux needed any software changes at all for the TLB semantics clarification, although that was largely just due to luck - we had mis-used the TLB earlier, and fixing that software bug we rewrote the page table handling to be more robust, which means that the spec update from Intel didn't affect us at all, afaik). </quip> -- sometimes truth is stranger than fiction -bad religion- http://www.bloglines.com/blog/mailist _________________________________________________ Philippine Linux Users' Group (PLUG) Mailing List [email protected] (#PLUG @ irc.free.net.ph) Read the Guidelines: http://linux.org.ph/lists Searchable Archives: http://archives.free.net.ph
