That is true, but even "lots" of registers is just a hundred or so. Latency to the L1 cache is generally only 1 clock cycle so having less registers is not as crippling as might be thought.
All current 32-bit x86 have lots and lots of registers anyway, they are just not user-visible. So for general workloads (lots of threads, lots of context switches) the number of user-visible registers probably doesn't make a huge difference. For single-thread, CPU-bound processes (not that many of those...) then yes, probably having more registers would help. On Nov 27, 2007 4:05 PM, Rafael Sevilla <[EMAIL PROTECTED]> wrote: > On Tue, 27 Nov 2007 15:45:42 +0800 > "Orlando Andico" <[EMAIL PROTECTED]> wrote: > > > This is not really true. When running in 64-bit mode, the cache is > > effectively halved. > > This is true, but I wonder how that balances out for CPU-intensive > code given the fact that the compiler has more registers to play with > when optimizing for 64-bit. A major problem with the x86 architecture > is its pitifully small number of registers, but this limitation has been > partially addressed in x86-64. _________________________________________________ Philippine Linux Users' Group (PLUG) Mailing List [email protected] (#PLUG @ irc.free.net.ph) Read the Guidelines: http://linux.org.ph/lists Searchable Archives: http://archives.free.net.ph
