CVSROOT: /cvs Module name: ports Changes by: [email protected] 2020/03/15 13:57:19
Modified files:
cad/openscad : Makefile
Log message:
Regen WANTLIB, double-conversion is back in qt5
CVSROOT: /cvs Module name: ports Changes by: [email protected] 2020/03/15 13:57:19
Modified files:
cad/openscad : Makefile
Log message:
Regen WANTLIB, double-conversion is back in qt5