CVSROOT: /cvs
Module name: ports
Changes by: [email protected] 2020/07/03 07:53:01
Log message:
Import qflow-1.4.83
OK sthen@, port from Alessandro De Laurenzis
Comment:
full end-to-end digital synthesis flow for VLSI ASIC designs
Description:
A digital synthesis flow is a set of tools and methods used to turn a
VLSI design written in a high-level behavioral language like Verilog
or VHDL into a physical circuit, which can either be configuration code
for an FPGA target or a layout in a specific technology, that would
become part of an IC.
Qflow uses a complete and open source tool chain for synthesizing
digital circuits starting from Verilog source and ending in physical
layout for a specific target fabrication process.
Maintainer: Alessandro De Laurenzis
WWW: http://opencircuitdesign.com/qflow/
Status:
Vendor Tag: rsadowski
Release Tags: rsadowski_20200703
N ports/cad/qflow/Makefile
N ports/cad/qflow/distinfo
N ports/cad/qflow/pkg/DESCR
N ports/cad/qflow/pkg/PLIST
N ports/cad/qflow/patches/patch-src_hash_c
N ports/cad/qflow/patches/patch-scripts_qrouter_sh
N ports/cad/qflow/patches/patch-src_vesta_c
N ports/cad/qflow/patches/patch-scripts_qflow_manager_py_in
N ports/cad/qflow/patches/patch-src_readlef_h
N ports/cad/qflow/patches/patch-scripts_magic_view_sh
No conflicts created by this import
