CVSROOT: /cvs
Module name: ports
Changes by: [email protected] 2010/07/08 12:58:23
Log message:
import iverilog 0.9.2
Icarus Verilog is a Verilog simulation and synthesis tool. It operates
as a compiler, compiling source code writen in Verilog (IEEE-1364) into
some target format. For batch simulation, the compiler can generate C++
code that is compiled and linked with a run time library (called "vvm")
then executed as a command to run the simulation. For synthesis, the
compiler generates netlists in the desired format.
Status:
Vendor Tag: jasper
Release Tags: jasper_20100708
N ports/lang/iverilog/Makefile
N ports/lang/iverilog/distinfo
N ports/lang/iverilog/pkg/DESCR
N ports/lang/iverilog/pkg/PLIST
No conflicts created by this import
