CVSROOT: /cvs
Module name: ports
Changes by: [email protected] 2011/09/16 02:13:12
Log message:
import freehdl 0.0.7
FreeHDL is a compiler/simulator suite for the hardware description
language VHDL. VHDL'93 as well as VHDL'87 standards are supported.
[...]
ok landry@
Status:
Vendor Tag: jasper
Release Tags: jasper_20111609
N ports/lang/freehdl/Makefile
N ports/lang/freehdl/distinfo
N ports/lang/freehdl/pkg/PLIST
N ports/lang/freehdl/pkg/DESCR
N ports/lang/freehdl/pkg/PFRAG.shared
No conflicts created by this import
