CVSROOT: /cvs
Module name: ports
Changes by: [email protected] 2011/09/16 07:46:13
Log message:
import myhdl 0.7
MyHDL is an open source Python package that lets you go from Python to
silicon. With MyHDL, you can use Python as a hardware description and
verification language. Furthermore, you can convert MyHDL code, that was
developed towards implementation, to Verilog and VHDL automatically, and
take it to a silicon implementation from there.
ok landry@
Status:
Vendor Tag: jasper
Release Tags: jasper_20111609
N ports/lang/myhdl/distinfo
N ports/lang/myhdl/Makefile
N ports/lang/myhdl/pkg/DESCR
N ports/lang/myhdl/pkg/PLIST
No conflicts created by this import
