CVSROOT: /cvs
Module name: ports
Changes by: [email protected] 2011/11/13 05:44:04
Log message:
import verilator-3.824
Verilator is the fastest free Verilog HDL simulator, and beats most
commercial simulators. It compiles synthesizable Verilog (not test-bench
code!), plus some PSL, SystemVerilog and Synthesis assertions into C++
or SystemC code. It is designed for large projects where fast simulation
performance is of primary concern, and is especially well suited to
generate executable models of CPUs for embedded software design teams.
ok aja@
Status:
Vendor Tag: jasper
Release Tags: jasper_20111311
N ports/lang/verilator/distinfo
N ports/lang/verilator/Makefile
N ports/lang/verilator/pkg/PLIST
N ports/lang/verilator/pkg/DESCR
No conflicts created by this import
