CVSROOT: /cvs
Module name: ports
Changes by: [email protected] 2018/08/08 09:24:47
Log message:
Import cad/abc, a system for sequential logic synthesis and verification.
Original submission from Alessandro De Laurenzis, who takes MAINTAINER --
thanks!
Additional work from sthen@ and myself, ok sthen@
ABC is a growing software system for synthesis and verification of binary
sequential logic circuits appearing in synchronous hardware designs. ABC
combines scalable logic optimization based on And-Inverter Graphs (AIGs),
optimal-delay DAG-based technology mapping for look-up tables and standard
cells, and innovative algorithms for sequential synthesis and verification.
Status:
Vendor Tag: bcallah
Release Tags: bcallah_20180808
N ports/cad/abc/Makefile
N ports/cad/abc/distinfo
N ports/cad/abc/patches/patch-Makefile
N ports/cad/abc/pkg/DESCR
N ports/cad/abc/pkg/PLIST
No conflicts created by this import
