CVSROOT: /cvs
Module name: ports
Changes by: [email protected] 2018/08/10 13:40:03
Log message:
import ports/cad/yosys, from maintainer Alessandro De Laurenzis, ok bcallah
Yosys Open SYnthesis Suite
Yosys is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains. Selected features and typical applications:
- Process almost any synthesizable Verilog-2005 design
- Converting Verilog to BLIF / EDIF/ BTOR / SMT-LIB / simple RTL Verilog /
etc.
- Built-in formal methods for checking properties and equivalence
- Mapping to ASIC standard cell libraries (in Liberty File Format)
- Mapping to Xilinx 7-Series and Lattice iCE40 FPGAs
- Foundation and/or front-end for custom flows
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the Yosys C++ code base.
Status:
Vendor Tag: sthen
Release Tags: sthen_20180810
N ports/cad/yosys/Makefile
N ports/cad/yosys/distinfo
N ports/cad/yosys/patches/patch-Makefile
N ports/cad/yosys/patches/patch-kernel_yosys_cc
N ports/cad/yosys/patches/patch-tests_tools_autotest_sh
N ports/cad/yosys/pkg/PLIST
N ports/cad/yosys/pkg/DESCR
No conflicts created by this import
