CVSROOT: /cvs
Module name: ports
Changes by: [email protected] 2019/03/27 02:45:25
Log message:
Import opensta-2.0.11.20190327.
OpenSTA is a gate level static timing verifier. As a stand-alone
executable it can be used to verify the timing of a design using
standard file formats:
- Verilog netlist
- Liberty library
- SDC timing constraints
- SDF delay annotation
- SPEF parasitics
From Alessandro De Laurenzis; thanks!
ok sthen@
Status:
Vendor Tag: bentley
Release Tags: bentley_20190327
N ports/cad/opensta/Makefile
N ports/cad/opensta/distinfo
N ports/cad/opensta/pkg/DESCR
N ports/cad/opensta/pkg/PLIST
No conflicts created by this import
