Patent pending. Quantum teleportation bus for FTL (faster than light) operations in multiple processor architecture
1024-bit architecture with 10-17 Qbit processors Serial supercomputing CPU:s with massive multithreaded architecture á la Sparc Niagra/AMD Ryzen working name sparcplug1024 Massive L2 cache High clock speed ~12.7 GHz per thread 256-8192 threads per core 16-64 Multiple on chip cores for optimal hardware and electrical performance 1-512 CPU:s per system, 16-64 cores each, 256-8192 threads per core = 4096 - 268435456 threads per physical system Systems can be combined through networking for practically infinite scaling L2 on chip error correcting/error detecting secondary memory ecDRAM at 512GB-262144GB L1 on quantum entanglement bus qecDRAM 8192GB-536870912GB primary error correcting/error detecting primary memory with Quantum FTL memory access Networking: Quantum Entanglement Internet/IP 4 physical Quantum Entanglement "teleportation" Ethernet, 4 ports per CPU Operating system: QSSysVI (Quantum Super System 6) Quantum L3 logic gate Quantum entanglement chip with "teleportation" access to other physical equivalent nodes Quantum entanglement chip with "teleportation" access to primary memory qecDRAM 10-17 Qbit processors á la Kookaburra There is not and isn't going to be qRAM because it wouldn't be deterministic Best regards, Jussi Korkala
