On Sun, Dec 28, 2025 at 10:28:58AM +0100, Peter Hessler wrote:
> On 2025 Dec 26 (Fri) at 18:00:50 +0100 (+0100), Jeremie Courreges-Anglas
> wrote:
> :On Fri, Dec 26, 2025 at 06:55:14AM +0100, Rafael Sadowski wrote:
> :> On Fri Dec 26, 2025 at 10:16:46AM +1100, Jonathan Gray wrote:
> :> > On Thu, Dec 25, 2025 at 11:57:16PM +0100, Peter Hessler wrote:
> :> > >
> :> > >
> :> > >
> :http://build-failures.rhaalovely.net/aarch64/2025-12-22/x11/qt6/qtwebengine.log
> :> > > :
> :> > >
> :> > > In file included from
> ../../../../../qtwebengine-everywhere-src-6.10.1/src/3rdparty/chromium/third_party/libaom/source/libaom/av1/encoder/arm/av1_error_sve.c:19:
> :> > >
> ../../../../../qtwebengine-everywhere-src-6.10.1/src/3rdparty/chromium/third_party/libaom/source/libaom/aom_dsp/arm/aom_neon_sve_bridge.h:15:10:
> :> > > fatal error: 'arm_neon_sve_bridge.h' file not found
> :> > > 15 | #include <arm_neon_sve_bridge.h>
> :> > > | ^~~~~~~~~~~~~~~~~~~~~~~
> :> >
> :> > The log shows base clang.
> :> >
> :> > Does installing the include fix the build?
> :>
> :> I tried to mix the headers from base and ports to get access to
> :> arm_neon_sve_bridge without luck. I would be grateful if we could do it
> :> that way. CC robert@
> :
> :FWIW I fixed Robert's mail address. A similar diff was already
> :proposed by Brad:
> :
> : https://marc.info/?l=openbsd-tech&m=174155733400782&w=2
> :
> :But it resulted in build failures using clang-19:
> :
> : https://marc.info/?l=openbsd-tech&m=174482865617988&w=2
> :
> :For this header addition to be a clear improvement we'd need to first
> :apply Brad's proposal which backports some code from llvm/20:
> :
> : https://marc.info/?l=openbsd-ports&m=174555990331066&w=2
> :
> :Regarding the diff below,
> :
> :> >
> :> > Index: gnu/usr.bin/clang/include/clang/intrin/Makefile
> :> > ===================================================================
> :> > RCS file: /cvs/src/gnu/usr.bin/clang/include/clang/intrin/Makefile,v
> :> > diff -u -p -r1.29 Makefile
> :> > --- gnu/usr.bin/clang/include/clang/intrin/Makefile 13 Jun 2025
> 17:11:09 -0000 1.29
> :> > +++ gnu/usr.bin/clang/include/clang/intrin/Makefile 25 Dec 2025
> 23:05:51 -0000
> :> > @@ -30,7 +30,7 @@ GEN+= arm_bf16.h
> :> > GEN+= arm_mve.h
> :> > GEN+= arm_cde.h
> :> > GEN+= arm_vector_types.h
> :> > -HEADERS+= arm_acle.h arm_cmse.h ${GEN}
> :> > +HEADERS+= arm_acle.h arm_cmse.h arm_neon_sve_bridge.h ${GEN}
> :
> :Brad's diff only installed the header on aarch64.
> :gnu/llvm/clang/lib/Headers/CMakeLists.txt indeed marks this file as
> :"aarch64-only" so I'd suggest we use Brad's diff.
> :
>
> Does someone have a complete diff I can test? I'm not sure what part
> from ports and what parts from src I need to use.
Here's the consolidated diff for base. I have checked that it fixes
the build of one of the ports that used to fail (I just don't remember
which one, maybe svt-av1).
Index: distrib/sets/lists/comp/clang.arm64
===================================================================
RCS file: /home/cvs/src/distrib/sets/lists/comp/clang.arm64,v
diff -u -p -r1.48 clang.arm64
--- distrib/sets/lists/comp/clang.arm64 8 Dec 2025 15:40:41 -0000 1.48
+++ distrib/sets/lists/comp/clang.arm64 28 Dec 2025 21:41:04 -0000
@@ -3200,6 +3200,7 @@
./usr/lib/clang/19/include/arm_fp16.h
./usr/lib/clang/19/include/arm_mve.h
./usr/lib/clang/19/include/arm_neon.h
+./usr/lib/clang/16/include/arm_neon_sve_bridge.h
./usr/lib/clang/19/include/arm_sme.h
./usr/lib/clang/19/include/arm_sve.h
./usr/lib/clang/19/include/arm_vector_types.h
Index: gnu/llvm/llvm/lib/CodeGen/TargetLoweringBase.cpp
===================================================================
RCS file: /home/cvs/src/gnu/llvm/llvm/lib/CodeGen/TargetLoweringBase.cpp,v
diff -u -p -r1.1.1.5 TargetLoweringBase.cpp
--- gnu/llvm/llvm/lib/CodeGen/TargetLoweringBase.cpp 11 Jun 2025 17:29:20
-0000 1.1.1.5
+++ gnu/llvm/llvm/lib/CodeGen/TargetLoweringBase.cpp 28 Dec 2025 23:06:50
-0000
@@ -1961,6 +1961,9 @@ void TargetLoweringBase::insertSSPDeclar
// Currently only support "standard" __stack_chk_guard.
// TODO: add LOAD_STACK_GUARD support.
Value *TargetLoweringBase::getSDagStackGuard(const Module &M) const {
+ if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
+ return M.getNamedValue("__guard_local");
+ }
return M.getNamedValue("__stack_chk_guard");
}
Index: gnu/llvm/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
RCS file:
/home/cvs/src/gnu/llvm/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp,v
diff -u -p -r1.5 AArch64ISelLowering.cpp
--- gnu/llvm/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp 11 Jun 2025
17:31:20 -0000 1.5
+++ gnu/llvm/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp 28 Dec 2025
20:58:41 -0000
@@ -2471,6 +2471,19 @@ MVT AArch64TargetLowering::getScalarShif
bool AArch64TargetLowering::allowsMisalignedMemoryAccesses(
EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags
Flags,
unsigned *Fast) const {
+
+ // Allow SVE loads/stores where the alignment >= the size of the element
type,
+ // even with +strict-align. Predicated SVE loads/stores (e.g. ld1/st1), used
+ // for stores that come from IR, only require element-size alignment (even
if
+ // unaligned accesses are disabled). Without this, these will be forced to
+ // have 16-byte alignment with +strict-align (and fail to lower as we don't
+ // yet support TLI.expandUnalignedLoad() and TLI.expandUnalignedStore()).
+ if (VT.isScalableVector()) {
+ unsigned ElementSizeBits = VT.getScalarSizeInBits();
+ if (ElementSizeBits % 8 == 0 && Alignment >= Align(ElementSizeBits / 8))
+ return true;
+ }
+
if (Subtarget->requiresStrictAlign())
return false;
Index: gnu/usr.bin/clang/include/clang/intrin/Makefile
===================================================================
RCS file: /home/cvs/src/gnu/usr.bin/clang/include/clang/intrin/Makefile,v
diff -u -p -r1.29 Makefile
--- gnu/usr.bin/clang/include/clang/intrin/Makefile 13 Jun 2025 17:11:09
-0000 1.29
+++ gnu/usr.bin/clang/include/clang/intrin/Makefile 28 Dec 2025 21:40:24
-0000
@@ -31,6 +31,9 @@ GEN+= arm_mve.h
GEN+= arm_cde.h
GEN+= arm_vector_types.h
HEADERS+= arm_acle.h arm_cmse.h ${GEN}
+.if ${MACHINE_ARCH} == "aarch64"
+HEADERS+= arm_neon_sve_bridge.h
+.endif
.elif ${MACHINE_ARCH} == "amd64" || ${MACHINE_ARCH} == "i386"
HEADERS+= __wmmintrin_aes.h \
__wmmintrin_pclmul.h \
--
jca
