Update the outdated DESCR in lang/iverilog; see http://www.icarus.com/eda/verilog/
Index: lang/iverilog/Makefile =================================================================== RCS file: /cvs/ports/lang/iverilog/Makefile,v retrieving revision 1.4 diff -u lang/iverilog/Makefile --- lang/iverilog/Makefile 17 Nov 2010 10:16:11 -0000 1.4 +++ lang/iverilog/Makefile 14 Mar 2011 06:01:19 -0000 @@ -5,6 +5,7 @@ V= 0.9.3 DISTNAME= verilog-$V PKGNAME= iverilog-$V +REVISION= 0 CATEGORIES= lang devel HOMEPAGE= http://www.icarus.com/eda/verilog/ Index: lang/iverilog/pkg/DESCR =================================================================== RCS file: /cvs/ports/lang/iverilog/pkg/DESCR,v retrieving revision 1.1.1.1 diff -u lang/iverilog/pkg/DESCR --- lang/iverilog/pkg/DESCR 8 Jul 2010 18:58:23 -0000 1.1.1.1 +++ lang/iverilog/pkg/DESCR 14 Mar 2011 06:01:19 -0000 @@ -1,12 +1,11 @@ Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into -some target format. For batch simulation, the compiler can generate C++ -code that is compiled and linked with a run time library (called "vvm") -then executed as a command to run the simulation. For synthesis, the -compiler generates netlists in the desired format. +some target format. For batch simulation, the compiler can generate an +intermediate form called vvp assembly. This intermediate form is +executed by the "vvp" command. For synthesis, the compiler generates +netlists in the desired format. The compiler proper is intended to parse and elaborate design -descriptions written to the IEEE standard IEEE Std 1364-2000. The -standard proper is due to be release towards the middle of the year -2000. This is a fairly large and complex standard, so it will take some -time for it to get there, but that's the goal. +descriptions written to the IEEE standard IEEE Std 1364-2005. This is a +fairly large and complex standard, so it will take some time for it to +get there, but that's the goal.
