On Wed, Sep 27, 2017 at 11:42:50AM +1000, Jonathan Gray wrote:
> On Tue, Sep 26, 2017 at 01:08:54PM -0700, Stephen Graf wrote:
> > I took this dtb from the amd64 dtb package yesterday (dtb-4.13.tgz).
> >
> >
> >
> > The address register for i2c01 and i2c02 are the same. I2c02 should be:
> >
> > reg = <0x1c2b400 0x400>;
>
> Talk to upstream on the devicetree list.
>
> Changes first went in with
>
> commit d8a507e6d9316b1023ba3cc9a7e696067200b495
> Author: Jorik Jonker <jo...@kippendief.biz>
> Date: Mon Sep 12 20:12:47 2016 +0200
>
> dts: sun8i-h3: add I2C0-2 peripherals to H3 SOC
>
> These peripherals can only be muxed to these pins, so they are
> associated in the DTSI instead of the board files. This makes it very
> easy to enable them using overlays or u-boot commands:
>
> => fdt set /soc/i2c@01c2ac00 status okay
>
> Signed-off-by: Jorik Jonker <jo...@kippendief.biz>
> Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
>
> in sun8i-h3.dtsi but later got moved to sunxi-h3-h5.dtsi.
Fixed in the following commit which is in master and should
be in 4.15-rc1.
commit 4d2ee8d56bdb17bf296800829642bbd34ef08a09
Author: Corentin LABBE <clabbe.montj...@gmail.com>
Date: Tue Sep 26 09:22:22 2017 +0200
ARM: dts: sunxi: h3/h5: Fix i2c2 register address
The unit address and register address does not match.
This patch fix the register address with the good one.
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Signed-off-by: Corentin Labbe <clabbe.montj...@gmail.com>
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 6c71d5aa6352..24a7a0c84449 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -575,7 +575,7 @@
i2c2: i2c@1c2b400 {
compatible = "allwinner,sun6i-a31-i2c";
- reg = <0x01c2b000 0x400>;
+ reg = <0x01c2b400 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C2>;
resets = <&ccu RST_BUS_I2C2>;
