Dear ports@ readers,
this should be considered a middle-term project.
Qflow [1] is an open-source digital synthesis flow developed by Open
Circuit Design. From its home page:
"A digital synthesis flow is a set of tools and methods used to turn a
circuit design written in a high-level behavioral language like verilog
or VHDL into a physical circuit, which can either be configuration code
for an FPGA target like a Xilinx or Altera chip, or a layout in a
specific fabrication process technology, that would become part of a
fabricated circuit chip."
To my knowledge, this is the only existing solution for VLSI circuits'
implementation entirely based on open-source tools, so its porting would
probably be beneficial to a number of users (by the way, I would love to
hear from anybody interested in testing it, for professional usage,
hobby projects, study or whatever).
The flow, like the topic, is complex and based on a number of tools;
some of them are integral part of the Qflow suite (*), some others are
developed or maintained by the same author (**), and finally there are
third-party (***) tools, not associated with the project, but officially
supported by the flow itself:
- RTL simulation: iverilog [2] (***), already in ports;
- logic synthesis: yosys [3] (***), requires abc [4] (***);
- placement: graywolf (***) [5];
- routing: qrouter (**) [6];
- layout viewer, parasitics extraction & DRC: magic (**) [7];
- LVS: netgen (**) [8];
- static timing analysis: vesta (*).
So my objective would be to import all missing tools, with the following
tree of dependencies:
Qflow
|
\_ yosys
| |
| \_ abc
|
\_ graywolf
|
\_ qrouter
|
\_ magic
|
\_ netgen
At the moment I have a complete suite compiled and running under
OpenBSD, lightly tested for amd64; most of the programs have patches (in
the configuration part as well as into the code), but building quality
grade ports is another story, considering that I'm neither a C
programmer nor a porter.
So I'll submit what I have, being completely open to modify (or even
redo from scratch) my proposals; when the patches become formally (and
hopefully functionally) correct, I'll propose them upstream.
Hope this activity will catch your attention and interest.
All the best
[1] http://opencircuitdesign.com/qflow/
[2] http://iverilog.icarus.com/
[3] http://www.clifford.at/yosys/about.html
[4] http://www.clifford.at/yosys/about.html
[5] https://github.com/rubund/graywolf/
[6] http://opencircuitdesign.com/qrouter/
[7] http://opencircuitdesign.com/magic/
[8] http://opencircuitdesign.com/netgen/
--
Alessandro DE LAURENZIS
[mailto:[email protected]]
Web: http://www.atlantide.t28.net
LinkedIn: http://it.linkedin.com/in/delaurenzis
