>-----Original Message----- >From: [EMAIL PROTECTED] >[mailto:[EMAIL PROTECTED] On Behalf Of Török Edvin >Sent: Thursday, June 21, 2007 3:20 AM >To: [email protected] >Subject: CPU C4 vs. C3 states, BIOS support and 1.5W power savings > >Hi, > >My system reports C3 as deepest sleep-state. Arjan once said on this >ML that the BIOS should remap C3 to C4. I made some experiments to >find out if my BIOS really did that or not. > >I have an ICH7-M (82801GBM) motherboard, downloaded the datasheet for >it (30701303.pdf), and on page 419 I see there is a bit C4onC3_EN in >GEN_PMCON_1 register, that does the remapping Arjan talked about. >Using lspci -xxx -s 00:1f.0 I found out that it was disabled (and so >was Intel SpeedStep)! > >So I did the following experiment (without the AHCI ALPM enabled): >Power consumption in default state : ~12 W >Turn on C4onC3_EN, and speedstep: setpci -s 00:1f.0 a0.w=a8 >Power consumption after >30s: 10.5W (1.5W savings!) >Turn off C4onC3_En: setpci -s 00:1f.0 a0.w=20 >Within seconds power consumption rises to 12 W > >[If somebody else wants to try this, make sure you read your chipset's >datasheet first!] > >Clearly this is something thats worth enabled, and I wonder why the >BIOS doesn't enable it.
Nice detective work ;-) Possibly BIOS only enables this on battery and disables on AC. There is a performance/latency penalty of using deeper C-state. >Reading through the datasheet, I find that there is a P_LVL4 register >that when read will make CPU enter C4 state. (page 439, LV4 register). >Its address can be find out from ACPI P_BLK+6. > >I see that Linux only support up to ACPI C3 (P_LVL3: P_BLK+5). A quick >glance at the ACPI spec tells me there is no ACPI C4. Is this LV4 >register on ICH7-M non-standard? >Would it be worth adding support for ACPI C4 (P_BLK+6) for >motherboards that support it , even if the BIOS won't report it in its >_CST tables? [My _CST table containts 3 C states for CPU0, and 1 >C-state for CPU1). > There are two different C-states. ACPI only has C0 and C1, C2, C3 defined and that is mostly related to the meaning associated with each state (things like whether cache snooping is done in a particular C-state or not) >BTW, Intel docs say CPU C4 state (which is not the same as ACPI >C-states?) is same as C3, unless _both_ cores enter C4, then the >package-level low-power mode will be activated. Maybe it would be >useful for powertop to show C-state usage for _both_ cores (i.e. if >they both entered C3/C4 or not)? > Hardware C-state can be anywhere along C0, C1, C2, C3, C4, C5,.... This is basically what a processor supports and each of those C-state will eventually map to a particular ACPI C-state depending on the behavior of CPU while in that state, as defined by ACPI. So, there can be C4 state that maps to ACPI C3 state, etc. >There are also extended C-states (C1E, C2E,...C4E) usable via MWAIT >eax hints register, but docs say the BIOS should activate these, but >it obviously doesn't (I don't even have C4, let alone C4E). Should I >venture in trying to use C4E, or will that void my warranty or >something like that? > Yes. Mwait hints should come from BIOS in ACPI _CST table. It is like the person building the platform gets to choose what features they want to support on the platform. So, changing anything in a way platform provider didn't intend to do may be a slippery slope. You should check with the platform providers and warranty providers :-). Thanks, Venki _______________________________________________ Power mailing list [email protected] http://www.bughost.org/mailman/listinfo/power
