On Wednesday 20 July 2005 23:12, John R Pierce wrote: > Brian Beesley wrote: > > On Wednesday 20 July 2005 20:02, Alex Phillips wrote: > >>For the purposes of Prime testing, dual-core processors behave exactly > >> like an SMP mobo with 2 CPUs fitted, however you only get half as much > >> memory bus bandwidth for each CPU, compared with a proper SMP mobo, > > > > Actually this is a memory controller issue. There are lots of "hobbyist" > > dual-cpu mobos which aren't "proper" i.e. have only one memory controller > > and are therefore subject to the sort of blocking you describe. > > how about every chipset and CPU Intel makes ?
High end servers (at least those using Xeons) should, and often do, have a memory controller per CPU, and multiported memory. It's the only sane way to organize a system with more than a few CPUs. Mind you we're talking big bucks... > > AMD Opteron processors have a shared memory controller per CPU. Intel Xeon > processors use a single shared memory bus in all normal configurations. > Yes, AMD building the memory controller into the CPU itself involves a performance compromise. You can still have an N-opteron mobo using multiported memory but non-cached memory accesses between "remote" CPUs will then probably be _faster_ than non-cached memory accesses between CPUs on the same chip. The complication is that cached memory may be shared between CPUs on the same chip. Can't have everything without having one socket per CPU, I guess. No, systems with lots of Xeons (certainly more than 4) pretty well have to use multiple memory controllers accessing multiported memory if they're not going to be completely crippled. Regards Brian Beesley _______________________________________________ Prime mailing list [email protected] http://hogranch.com/mailman/listinfo/prime
