> Is there a reason to prefer Vdd over GND?  The spec sheets often just say
> "tied high or low...", and my knowledge of theory is too weak to even
guess
> at an answer. :)
> TIA,
> Dwight Harm.


Dwight,
Here is my guess,   the input of a cmos circuit (inside of the IC) though it
has a high input impedance to gnd, they have an internal resistor internally
tied from the gate to Vdd.  Tying the gate to gnd in most devices is when
input current is actually sinking into the device and most inputs to
devices are not  actually on when they are applied with a voltage.   Reverse
of the way you may think.  Draw the circuit out and then tell me when the
most current is being sunk thru the input.  By tying the input to gnd and
not vcc you are actually sinking current in the device input path.   May not
sound like a lot of current for most applications, but for some critical
applications like spacecraft where power is a premium tying inputs "hi" is
mandatory design criteria.  So tying hi or lo does make a  difference.

Mike Reagan
EDSI
Frederick

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