Asymmetric input current is a characteristic of the TTL logic family but is not the 
case for CMOS.
Even TTL compatible CMOS (eg. ACT or HCT families) has a symmetric and very high input 
impedence (leakage currents of less than 1 uA) for both low and high inputs.  TTL 
compatibility is accomplishied by shifting the logic threshold down to between 0.8V 
and 2.0V instead of the normal CMOS threshold of one half of the supply voltage.

John Williams



Mike Reagan wrote:

> Here is my guess,   the input of a cmos circuit (inside of the IC) though it
> has a high input impedance to gnd, they have an internal resistor internally
> tied from the gate to Vdd.  Tying the gate to gnd in most devices is when
> input current is actually sinking into the device and most inputs to
> devices are not  actually on when they are applied with a voltage.   Reverse
> of the way you may think.  Draw the circuit out and then tell me when the
> most current is being sunk thru the input.  By tying the input to gnd and
> not vcc you are actually sinking current in the device input path.   May not
> sound like a lot of current for most applications, but for some critical
> applications like spacecraft where power is a premium tying inputs "hi" is
> mandatory design criteria.  So tying hi or lo does make a  difference.

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