Dwight Harm wrote:

> Is there a reason to prefer Vdd over GND?  The spec sheets often just say
> "tied high or low...", and my knowledge of theory is too weak to even guess
> at an answer. :)

Sometimes it doesn't matter, as in a completely unused gate.  Sometimes it
does matter, such as a completely unused flip-flop, where you would not
want to tie both the reset and set inputs to their active level, as that would
cause that flip-flop to be in a meta-stable state, which could cause
oscillation or upset the performance of the other FFs in the same package.

In TTL and LSTTL, ground is preferred, as you can ground an input
without any limiting resistor. This does increase current draw of the
chip slightly, however.  To stop that, and in cases where a static input
needs to be at a high level, it is suggested that a 1K Ohm resistor be
placed in series with the input, so that if the +5 V power supply goes to
an abnormally high voltage, the chip may survive up to 7 Volts or so.
Without the resistor, the input protection network would pop at about
5.5 V.  All this is for TTL and LS related families, and does not really
apply much to CMOS.

Jon

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