It is unlikely that tying an input high or low makes much of a difference on
current consumption, with the exception of a uP with internal pull-ups
enabled.  You have to look at what the input goes to.  Spare gates -
probably no difference.  uP pins, depends on if it changes the operation of
the chip in an undesirable way.  In most cases, if it makes no difference to
the chip, whatever may make the PCB layout easiest (annotate to SCH), or
makes using the input later (with a wire?) easier.

-----Original Message-----
From: Dwight Harm [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, March 28, 2001 3:09 PM
To: 'Protel EDA Forum'
Subject: [PEDA] OT: Unused CMOS inputs (was: Reference)


Is there a reason to prefer Vdd over GND?  The spec sheets often just say
"tied high or low...", and my knowledge of theory is too weak to even guess
at an answer. :)
TIA,
Dwight Harm.

> -----Original Message-----
> From: Andy Gulliver [mailto:[EMAIL PROTECTED]]
> Sent: Wednesday, March 28, 2001 6:52 AM
> Subject: Re: [PEDA] Reference
<snip>
> Unused inputs should ideally be pulled to Vdd via a suitable resistor
> (opinions vary, but 10k-100k should suffice).  A number of inputs can be
> linked and pulled up by the same resistor to cut the number of resistors
> needed (if cost/space is critical) but watch out for pull-up traces
running
> long distances...

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