At 03:08 PM 3/28/01 -0800, Dwight Harm wrote:
>Is there a reason to prefer Vdd over GND?  The spec sheets often just say
>"tied high or low...", and my knowledge of theory is too weak to even guess
>at an answer. :)

Someone correct me if I am wrong, but my understanding is that it does not 
matter with CMOS. The tradition of using a pull-up resistor instead of a 
pull-down comes from TTL practice where it did make a difference, since TTL 
draws more current when an input is grounded.

I'd think that one could ground unused inputs of CMOS gates and have no 
risk of overvoltage on the inputs during power-up. But I've connected open 
CMOS to VCC many many times without a peep of complaint.

[EMAIL PROTECTED]
Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433

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