I recently ran into that too.  You could try a global search & replace on
the net names to change all the labels in your schematic you are importing
to match up with your current design.

_____________
Brian Guralnick



----- Original Message -----
From: "David Cary" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Thursday, April 05, 2001 12:48 PM
Subject: Re: [PEDA] Bus nets


>
>
>
>
> Dear Brad Velander,
>
> This is an interesting idea.
>
> I don't think it will work directly, because in Protel a net has only one
name.
> Protel gives me an error when I try to put 2 different netlabels on the
same
> wire.
>
> But others have suggested a "virtual short" schematic component that can
be used
> to connect 2 different nets together. Would that work here ? (It's a tiny
little
> box with 2 short pins that *look* like they short together on the
schematic
> printouts, but ERC thinks they don't, so everyone is happy). (It has a
"virtual
> short" footprint that actually does short together when the PCB is
manufactured,
> but DRC thinks it doesn't, so everyone is happy).
>
> Say I have, say, SCK and SDA and I want to run it out one port (using SCK
=
> Ser1, SDA=Ser2) onto another schematic sheet. Do I get any warning if I
> accidentally swap them (SCK=Ser0, SDA=Ser1) ?
>
>
>
>
>
> Brad Velander <[EMAIL PROTECTED]> on 2001-04-05 10:39:41 AM
>
> Please respond to "Protel EDA Forum" <[EMAIL PROTECTED]>
>
> To:   "'Protel EDA Forum'" <[EMAIL PROTECTED]>
> cc:    (bcc: David Cary/TULSA/BRUNSWICKOUTDOOR)
>
> Subject:  Re: [PEDA] Bus nets
>
>
>
>
> Reading this thread, I can't help but ask if something I used to do back
> many years ago in Orcad would work with Protel for buses. I also used to
> deal with bussing large numbers of control signals in Orcad. It was not
that
> hard to do with Orcad because it would eloquently handle multiple netnames
> on nets. It would even supply a list of renamed or multiply named nets in
> the ERC report so you could check for any mismatches in multiply named
nets.
> To bus control signals I handled it in the following manner, does this
work
> in Protel, I don't have time right now to give it a thorough test.
>      Name your control signals as normal while they are separate signals,
> close to the originating ICs. Just before you enter a bus, assign a new
> netname with an arbitrary sequential naming (i.e. B1, B2, B3..., C1, C2,
> C3...). Name the bus B1..3 or C1..3. When you break a signal out of the
bus
> again assign the sequential naming immediately when leaving the bus, then
> later along the individual signal rename it again to the control signal
> name.
>      Used to work just fine in Orcad, does it work for Protel? It could
> cause some minor confusion to the un-initiated but after a minute or two
and
> a brief explanation, everyone worked with it just fine.
>
> Sincerely,
>
> Brad Velander
>
>
>
>
>
>
>
>


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