On 03:08 PM 28/03/2001 -0800, Dwight Harm said:
>Is there a reason to prefer Vdd over GND?  The spec sheets often just say
>"tied high or low...", and my knowledge of theory is too weak to even guess
>at an answer. :)
>TIA,
>Dwight Harm.

Doesn't matter - insignificant effect on leakage current.

In the old days of LS and S logic the tie direction and resistance was 
important.

With HCMOS/ACMOS etc the tie direction doesn't make any significant 
difference (in either case the circuit looks like a reverse biased diode 
(the protection network) and the gates of two MOSFETs (unless the leakage 
across these is minute the device is broken).

It is recommended by some that a resistor be used to tie the gate - this is 
to support easier modification should the input be required later.  Not all 
products can afford the space and small $ increase of this but it is a good 
idea to at least consider.

Ian Wilson

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