Tie to ground would be my vote as it does not draw any current (tiny as it is).
Manufacturers
IDDQ tests done on wafers always tie low and pass levels are in the 100's of
nanoamp
range for some devices.
_______________________________________________________________
Clive Broome
IDT Sydney Design Centre Ph: +61 2 9763 3513
8 Bayswater Dr, Homebush Fax: +61 2 9763 3409
Sydney, NSW, 2127 Email:[EMAIL PROTECTED]
Australia
Australia's Leading Semiconductor Designers
---------------------------------------------------------------
"Dwight Harm" <[EMAIL PROTECTED]> on 03/29/2001 09:08:46 AM
Please respond to "Protel EDA Forum" <[EMAIL PROTECTED]>
To: "'Protel EDA Forum'" <[EMAIL PROTECTED]>
cc: (bcc: Clive Broome/sdc)
Subject: [PEDA] OT: Unused CMOS inputs (was: Reference)
Is there a reason to prefer Vdd over GND? The spec sheets often just say
"tied high or low...", and my knowledge of theory is too weak to even guess
at an answer. :)
TIA,
Dwight Harm.
> -----Original Message-----
> From: Andy Gulliver [mailto:[EMAIL PROTECTED]]
> Sent: Wednesday, March 28, 2001 6:52 AM
> Subject: Re: [PEDA] Reference
<snip>
> Unused inputs should ideally be pulled to Vdd via a suitable resistor
> (opinions vary, but 10k-100k should suffice). A number of inputs can be
> linked and pulled up by the same resistor to cut the number of resistors
> needed (if cost/space is critical) but watch out for pull-up traces
running
> long distances...
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