this is getting convoluted, so only a few comments [which usually means I
am about to write a tome]:
At 09:28 AM 4/6/01 -0700, Brad Velander wrote:
> You are comparing a bad experience with a complex tangled mess
>against my orderly and controlled methodology. Not exactly a fair
>comparison. Obviously you didn't use the ERC facility to check your
>interconnections either, although in this case it was obviously such a mess
>it probably wouldn't have helped you. With your experience of a mess as
>awful as this sounds, I don't blame your reaction but don't bleed all over a
>successful disciplined use of similar functions.
I'm an ERC fanatic. Yes, we ran ERC, and, yes, it was useless in finding
these errors. The errors, in fact, represented OrCAD bugs, in my opinion.
It's true that a bad experience like this is not a reason to condemn a
One of the big concepts of why open net renaming was allowed was precisely
for design re-use. So I wouldn't blame the engineers for trying to use the
tool in a way it was, in fact, designed to be used. And it would have
worked if there were more control in the tool. So if we are to propose that
Protel allow net renaming to form a control bus, as an example, I'd want to
know exactly how this would work; it would need some controls, perhaps a
detailed net renaming report that shows how nets were configured.
The renaming should be done in a special way so that ordinary net shorts
are confused with deliberate renames.
But do we really need this? Read on....
> > Why not just place a port on the wire in the first place,
> > called WR*? And
> > another, RD*, etc.
> Simple, in some cases you would have 30 - 40 various control signals
>drawn around various sheets and connecting sheet to sheet.
However, even with net renaming, that is what we will have. The difference
is only that a bus can be used to take the nets off a sheet as a single
port. Otherwise, sheet connection is, in fact, just a bunch of net names
scattered around the sheet. The drawn bus lines are to help the eye; they
are mostly not electrically functional. If you forget to draw the bus line,
the netlist will not change.
So, why not just draw this control bus? What one would have would be net
names like RD* and WR* implementing connectivity, and a bus line, which
might or might not be named, showing them as being organized together. At
the end of this bus, presumably on the left side of the page if the signals
are driven off-page, or on the right if they source on the page, there
would be a block of ports with the names of each net, one to a port.
So a sheet symbol on the next level up would show a block of these ports;
they would presumably be placed together; perhaps another cosmetic bus line
would be drawn on that sheet.
All one would really save by renaming WR*, RD*, etc., to CONTROL1,
CONTROL2, etc. is that there would be only one port instead of a block of
ports. I don't think that CONTROLn adds readability, in fact, because a
need to translate impairs readability.
The point I am making is that if you want a bus line for clarity, by all
means put one in. Thus this argument is seen to be misdirected:
> Why do you BUS
>data or address signals? For simplicity and clarity, easy to follow
>connections without 20 - 30 criss-crosses or bends and joints where your eye
>wonders onto another connection and to save sheet space. By your argument
>above, I would take it that you don't bus data or address signals? I don't
>think so. The reasons for doing this was a simple extension of the same
>reasoning for bussing data or address signals.
The difference, to be clear, between data and address signals and control
signals is that the former are easily described by a numerical sequence,
whereas the latter would require some translation to make them into a
numerical sequence. No translation is required to understand that ADDR3 is
part of ADDR[0..7].
> It is clear that you just don't understand this concept, what is
>confusing about a small netlabel just before the signal enters the bus, used
>only to configure the signals in a manner such that they can be bussed?
It's confusing because it is *extra*. It really adds no information. *The
bus lines add information.* But you don't have to rename nets to use a bus
>when it breaks out of the bus, another small netlabel which breaks it
>correctly out of the bus structure. Then a little further down the net is
>the proper netname as usual, be it RD/W\R\ or whatever. You simply ignore
>the C1, C2, etc., where it enters the bus named C1..#. I used this system
>for years and years across several employers, not one person ever had a
>problem or issue with it, not even the stupidest engineers or techs I have
>ever worked with.
The question is not whether or not such a schematic is readable. I'm sure
it is readable. However, I doubt, seriously, that is as readable as the
*same* schematic, only the translated names are eliminated, and the ports
expanded. The bus lines can be left in to maintain the improved functional
readability. Now, on the next level up, I have a sheet symbol. With Mr.
Velander's system, there is a single sheet entry on thatt symbol,
CONTROL[C1...]. I'm looking at this sheet. What is C2? In order to find
out, I have to look back at the source sheet. If Mr. Velander has placed
net renames on this higher level sheet, then it might not be difficult, to
identify it, especially if the renames are right next to the sheet entry.
But that means that one has just named all the nets. Why not just leave
them with those names in the first place, so that the control signals
appear directly on the sheet symbol?
If there are forty of these signals, do I really want to have to convert
them to a number and then back in order to understand what they are doing?
Yes, if there is a net renaming report, it would become fairly easy to
check the net renaming. But that is an entirely unnecessary step if one
does not use renaming in the first place.
Protel forces a discipline with nets. Nets can be renamed across levels in
a hierarchy, but on one sheet, an error is generated. That error can be
suppressed, so one can do what Mr. Velander wants. Maybe. I just don't
think it's a good idea. Mr. Velander's argument was based on comparison
between a control bus with scattered renamed nets vs. *no* bus with
scattered nets. But that is an unfair comparison.
P.O. Box 690
El Verano, CA 95433
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