On Fri, 6 Apr 2001 09:28:23 -0700 , Brad wrote:

>       It is clear that you just don't understand this concept, what is
>confusing about a small netlabel just before the signal enters the bus, used
>only to configure the signals in a manner such that they can be bussed? Then
>when it breaks out of the bus, another small netlabel which breaks it
>correctly out of the bus structure.

The Cadence schematic stuff I have used a little works like this. Every bus
entry/exit has a numeric tag to identify which member of the bus you are
connecting. Busses can also be split and merged again with numeric range
tags. Symbols can even have bus 'pins' a whole 48 bit data bus on a
component can be connected directly to a bus (obviously no pin number
information shown). 

It is up to you to get the numeric tags right which possible source of
error. 

It works, I am not suggesting it is a good solution. 


I just went back through my archives and we had almost the same discussion
here 13 months ago.

What I proposed then (as a pretty simple thing for Protel to do) was to
extend the syntax of bus labelling to allow a list of nets including
ranges. 

Like on one sheet a bus with port would be 

  _____nWR,nRD,D[0..15]________| C[0..17] >

busses are still cosmetic, connections to the bus are by (local) net names.

You can wire this bus across a hierarchy and on destination sheets have
something like 

| C[0..17]> ______notWR,notRD,DATA[0..15]_______


On a higher level sheet you could also have something like


| C[0..17] >_____X[0..17]_______

_______X[0..1],X[10..17]______| G[0..9]>

_______X[0..1],X[2..9]________| G[0..9]>

Again the names do the connecting within that sheet, and 2 control + 16
data bit bus is split into 2 x 8 bit versions to feed identical sheets in a
complex heirarchy. 

I think something like this gives a lot of extra capability without any
fundamental changes or breaking any existing schematics. 








Cheers, Terry.


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