As a few people have said, on CMOS it doesn't make a lot of difference
electrically whether you pull to Vcc or GND (unless, as Steve Green said,
you might need to do a 'two cuts and a link' job with open-drain outputs as
a board fix - not that we've ever had to do any of those, Steve?).

With TTL it did matter which way the input was pulled, and I guess that old
habits die hard so it is indeed one of these things that's 'always been done
like that'.

> -----Original Message-----
> From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]]
> Sent: 29 March 2001 01:34
> To: Protel EDA Forum
> Subject: Re: [PEDA] OT: Unused CMOS inputs (was: Reference)
>
>
> At 03:08 PM 3/28/01 -0800, Dwight Harm wrote:
> >Is there a reason to prefer Vdd over GND?  The spec sheets often just say
> >"tied high or low...", and my knowledge of theory is too weak to
> even guess
> >at an answer. :)
>
> Someone correct me if I am wrong, but my understanding is that it
> does not
> matter with CMOS. The tradition of using a pull-up resistor instead of a
> pull-down comes from TTL practice where it did make a difference,
> since TTL
> draws more current when an input is grounded.
>
> I'd think that one could ground unused inputs of CMOS gates and have no
> risk of overvoltage on the inputs during power-up. But I've
> connected open
> CMOS to VCC many many times without a peep of complaint.
>


Good point.  Also, in reality with modern PSUs and in commercial
applications the chance of Vcc going far enough out of spec. to cause a
problem is remote.  The pull-up was a mandatory design rule in my early
circuit design days working on military avionics (54LS series TTL!) and I
still prefer it to a direct tie, although mainly to facilitate circuit
changes.


> [EMAIL PROTECTED]
> Abdulrahman Lomax
> P.O. Box 690
> El Verano, CA 95433


Regards

Andy Gulliver

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