Mike Reagan wrote:

> > Is there a reason to prefer Vdd over GND?  The spec sheets often just say
> > "tied high or low...", and my knowledge of theory is too weak to even
> guess
> > at an answer. :)
> > TIA,
> > Dwight Harm.
>
> Dwight,
> Here is my guess,   the input of a cmos circuit (inside of the IC) though it
> has a high input impedance to gnd, they have an internal resistor internally
> tied from the gate to Vdd.

No, if you check this with a DVM, you will find there is NO resistor
to either power rail on generic 4xxx, 74C, 74HC, etc. type chips, and
on most CMOS FPGAs, CPLDs, etc.  Those inputs have 100+ Meg Ohm
resistances, due to microscopic leakages on the protection diodes, mostly.
Only in very special cases would there be any intentional pull-up or pull-down
on a specific pin, for some special purpose.

>  Tying the gate to gnd in most devices is when
> input current is actually sinking into the device and most inputs to
> devices are not  actually on when they are applied with a voltage.   Reverse
> of the way you may think.  Draw the circuit out and then tell me when the
> most current is being sunk thru the input.  By tying the input to gnd and
> not vcc you are actually sinking current in the device input path.   May not
> sound like a lot of current for most applications, but for some critical
> applications like spacecraft where power is a premium tying inputs "hi" is
> mandatory design criteria.  So tying hi or lo does make a  difference.

This is certainly true in TTL, LS, etc., and the currents are NOT small at
all.  A grounded TTL input will sink 1.6 mA out of each input!  That can
add up quick on battery powered or other low power equipment.  Of
course, they DON'T use that stuff in battery powered gear anymore.

Jon

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