Mike Reagan wrote:

> Here is my guess,   the input of a cmos circuit (inside of the IC) though it
> has a high input impedance to gnd, they have an internal resistor internally
> tied from the gate to Vdd.

If that is really the case, then you do not need to tie the input external to
the chip :-)   The internal pullup resistor will pull the input to a high
state.  The reality is that except in certain chips like FPGAs, CPLDs and
microprocessors, the inputs do not have any pull-up/pull-down resistors.  You
can tie it high, or tie it low, whatever is convenient.

As for the resistor, it is necessary for bed of nails testers.  If the tester
wants to inject a high or a low on a pin which has been directly tied to a power
supply (ground or v+), it is out of luck.  That said, far more people go the
resistor route because "that is the way think it is supposed to be done"  than
for any legitimate reason like a bed of nails tested.

Hamid


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