Are you describing something like:

mainbus[A31..A0,nRD,nW,nRS,D15..D0]  -> so that there is a mainbusA0 ...
mainbusA31, mainbusnRD, mainbusnW, mainbusnRS, mainbusD15 ... mainbusD0.

or:

mainbus_*  -> where anything after mainbus_ becomes part of the mainbus_

or:

having predefined structures in separate ASCII files:

mainbus[structure ("motorola68030.def")]     -> now mainbus would contain
all the buss signals of the 030, from addrs, data & controls.
idebus1[structure ("StandardIDEbus.def")]     -> now mainbus would contain
all the buss signals of the standard IDE hd controller.


I think that all 3 possibilities have applications.

_____________
Brian Guralnick



----- Original Message -----
From: "Ian Wilson" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Monday, April 09, 2001 1:15 AM
Subject: Re: [PEDA] Bus nets


> On 09:04 PM 8/04/2001 -0700, Abd ul-Rahman Lomax said:
> <..snip..>
> >So, why not just draw this control bus? What one would have would be net
> >names like RD* and WR* implementing connectivity, and a bus line, which
> >might or might not be named, showing them as being organized together. At
> >the end of this bus, presumably on the left side of the page if the
> >signals are driven off-page, or on the right if they source on the page,
> >there would be a block of ports with the names of each net, one to a
port.
> >
> >So a sheet symbol on the next level up would show a block of these ports;
> >they would presumably be placed together; perhaps another cosmetic bus
> >line would be drawn on that sheet.
>
> I do this - it is not ideal but it works for now.  There could easily be a
> better method though - read on...
>
>
> ><..snip..>
> >The point I am making is that if you want a bus line for clarity, by all
> >means put one in. Thus this argument is seen to be misdirected:
>
> On a side note: slightly inflammatory words there -  "misdirected".  Your
> post has a bit of a feel of lecturing about it.
>
> Anyway, I think multiple net names will always be more confusing than one
> net name - lets make the bus function more flexible rather than introduce
> an unnecessary construct to get around an existing limitation.  I,
> personally, would be against multiple net naming being supported even as
an
> option.  One reason would be the possibility of mucking up the renaming so
> that nRD became nWR on one of the other sheets through some not-so-careful
> copy and paste.
>
> I *would* like the ability to collect multiple non-bus signals into a
> "collection".  A collection of nets would simply be a named list of
> nets.  Currently it is the bus net label (ADDR[0..31]) that carries the
> connectivity.  I would like the bus entries and the bus wire to assume a
> greater role such that the bus knows what nets it is carrying by knowing
> what bus (collection or whatever) entries have been made to it.  Then the
> net label is simply an alias for the list of nets.  The list is produced
> automatically by the netlister by noting what nets made a valid connection
> to the collection.  A bus would simply become a special case of a
> collection.  So now I can have a bus-sort-of-thing labelled ControlBus, or
> I2CBus and use it to pass this collection of nets around without
cluttering
> up the top level hierarchy or the left and right edges of my schematics.
>
> Allowing net classes to be defined in Sch would possible also allow an
> alternative method of creating named collections (this time the list of
> nets in the collection is being created manually).  (Would it be an ERC
> error if a net not belonging to the class
> attempted to connect to the collection?  I think yes.  If the collection
> name corresponds to a net class then only nets in that net class can
> connect to the collection  without generating an ERC.  This gets us
further
> along the way to a rules based Schematic editor.)
>
> I can't imagine that this would be that hard to implement - it is along
the
> lines of something I requested (verbally) many years ago.
>
> Ian Wilson
>
>
>
>


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