At 09:14 AM 4/9/01 -0700, Brad Velander wrote:
>Abd-ul Rahman,
>         just to clarify one issue, the nets would be renamed again upon any
>sheet where they were used or appeared as individual nets, as soon as they
>exit the bus structure. I didn't know that this was not implicit in my
>previous descriptions.

Yes, it was implicit; that is, when I responded, I noted that if they were 
*not* renamed, schematic interpretation would be difficult. I assumed you 
would, in fact, rename them back to the original names. Of course, you 
might *not* use the original names for some reason, by error or intention. 
And that's where things could get really hairy.

>  The only memory exercise is required when renaming
>the ports upon entry or exit from the bus structure. The only person who
>practices this memory exercise is the schematic editor and I would commonly
>copy chunks of the bus entry/exit to ensure correct matching of signal

Good. That would be the way to do it. Now, later, one discovers an error on 
one sheet and changes the name of one net. In some cases, you may have to 
remember to change it on the other sheet(s).

>         Your point #3 below does have significant merit but 'personally' I
>would not like to use of blocks of port symbols. Again it would just lead to
>clutter as well as leading to possible errors where a port or sheet symbol
>is missed/misspelled/misplaced. Using the method I have described there is
>one control signal port symbol reducing clutter and saving sheet real

It reduces clutter at the expense of increased complexity, in my view. 
Renaming the signals takes real estate, about the same real estate as would 
the ports. Sure, your sheet symbol, if you are using a hierarchical 
schematic, could be smaller, but at the expense of having the signals used 
on that sheet not being fully named *on the symbol*. And then space is 
taken outside the symbol to rename the nets. One might have some feature 
whereby clicking on the control bus would pop up a list of names, but that 
doesn't work with printed copies.

>         I too apologize if my remarks have seemed too critical or cutting, I
>could not understand why you were so critical of this system when I have
>previously had good experiences using it. I now think I understand why you
>thought there were possibly more problems with it then there really are,
>because of my explanation above.

The explanation given was already understood. My suspicion is that the 
"good experience" was caused by the improvement in readability by using a 
control bus, which is fully addressed by using a dummy bus. There is no 
clutter resulting from the explicit signal names themselves, as ports, that 
does not also exist in the bus-renaming system. Only if one thought that 
one must draw each individual control line as a wire would there be such 

I don't draw individual lines for control signals, usually. Rather I just 
use net labels on a short wire from the part. If there were many of these 
signals, I might make a dummy bus, but I've not recently seen a strong 
enough need for it to actually do this.

To the netlister, the bus lines, for the most part, don't exist. They are 
purely for the eye of the reader. (There is an exception, see below.). If 
you drew two buses, one ADDR[0..15] and one DATA[0..7], and then pulled 
DATA3 off of the drawn ADDR[0..15] bus, by mistake, no change would take 
place to the netlist and no error would be created. Unless, of course, 
DATA3 went to an address input....

The exception to the netlist irrelevancy of bus lines occurs when a bus 
port connects to a bus on a sheet. I think in this case there must be a bus 
label on the bus line directly connected to the port.

My apologies to those who are not using a monospaced font:

I fail to see

<CONT[1..4]>_CONT[1..4]             _______________
                        \_CONT1_WR*_/     |         | 

                        \_CONT2_RD*_/      \__WR*    \__RD*

as an improvement over

                                          |         | 

                                           \__WR*    \__RD*

though it may well be an improvement over discrete wires connected to the 
ports in the second case, or -- maybe -- over the second case with no dummy 
bus. But those are straw men.

Of course, there might well be a schematic where improvement over the use 
of a dummy bus is realized; just because I can't think of the situation 
doesn't mean that it doesn't exist.

I understand that Mr. Velander has his personal preferences, as do we all. 
But the bus renaming scheme was proposed as something that, if it were made 
easier, would improve Protel, and thus it becomes fair game for criticism. 
I don't agree. Yet. Perhaps someone could send me a schematic where I could 
see the improvement.

Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433

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