On 10:41 AM 11/04/2001 +1000, John Haddy said:
>However, the coponent clearance rule is next to useless once
>you start working with tightly packed boards. If you want to
>place componnets so that their silkscreen borders overlap
>(e.g. 0402s places side by side), you need to turn off the
>component clearance rule - so you end up with the very dangerous
>situation of requiring manual checking of each and every component
>placement.
What about allowing support for negative component clearances? So you can
define an allowed overlap between, for example, 0402 components. I agree
that in cases where a defined overlap is permissible that the extra layer
would be very helpful but I suspect will not happen in the next SP. I am
thinking about what could be implemented in SP7 easily here. Allowing
negative clearances should not be hard.
>I've said this before (but I'll repeat it in the hope that someone
>at Protel listens :-):
>
>What is really needed is an extra layer defined as a physical
>component outline layer. A clearance rule based on this layer would
>ensure that components did not try to physically occupy the same
>space. This rule would need to be combined with clearance rules that
>would ensure minimum gap between a primitive entity (e.g. pad, or
>a soldermask opening) and entities on the silkscreen layer (so that
>one component's legend doesn't end up over a pad).
Yep - there is a lot to think about in implementing this suggestion, new
rules that I can think of:
1) Minimum solder mask width (a bit like checking for internal plane
connectivity)
2) Overlay near pads (as you mentioned)
3) others
bye for now,
Ian Wilson
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